1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfh < %s \ 3; RUN: | FileCheck --check-prefix=RV32IZFH %s 4; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+experimental-zfh,+d < %s \ 5; RUN: | FileCheck --check-prefix=RV32IDZFH %s 6; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfh < %s \ 7; RUN: | FileCheck --check-prefix=RV64IZFH %s 8; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+experimental-zfh,+d < %s \ 9; RUN: | FileCheck --check-prefix=RV64IDZFH %s 10 11define half @f16_positive_zero(half *%pf) nounwind { 12; RV32IZFH-LABEL: f16_positive_zero: 13; RV32IZFH: # %bb.0: 14; RV32IZFH-NEXT: fmv.h.x fa0, zero 15; RV32IZFH-NEXT: ret 16; 17; RV32IDZFH-LABEL: f16_positive_zero: 18; RV32IDZFH: # %bb.0: 19; RV32IDZFH-NEXT: fmv.h.x fa0, zero 20; RV32IDZFH-NEXT: ret 21; 22; RV64IZFH-LABEL: f16_positive_zero: 23; RV64IZFH: # %bb.0: 24; RV64IZFH-NEXT: fmv.h.x fa0, zero 25; RV64IZFH-NEXT: ret 26; 27; RV64IDZFH-LABEL: f16_positive_zero: 28; RV64IDZFH: # %bb.0: 29; RV64IDZFH-NEXT: fmv.h.x fa0, zero 30; RV64IDZFH-NEXT: ret 31 ret half 0.0 32} 33 34define half @f16_negative_zero(half *%pf) nounwind { 35; RV32IZFH-LABEL: f16_negative_zero: 36; RV32IZFH: # %bb.0: 37; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0) 38; RV32IZFH-NEXT: flh fa0, %lo(.LCPI1_0)(a0) 39; RV32IZFH-NEXT: ret 40; 41; RV32IDZFH-LABEL: f16_negative_zero: 42; RV32IDZFH: # %bb.0: 43; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0) 44; RV32IDZFH-NEXT: flh fa0, %lo(.LCPI1_0)(a0) 45; RV32IDZFH-NEXT: ret 46; 47; RV64IZFH-LABEL: f16_negative_zero: 48; RV64IZFH: # %bb.0: 49; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0) 50; RV64IZFH-NEXT: flh fa0, %lo(.LCPI1_0)(a0) 51; RV64IZFH-NEXT: ret 52; 53; RV64IDZFH-LABEL: f16_negative_zero: 54; RV64IDZFH: # %bb.0: 55; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_0) 56; RV64IDZFH-NEXT: flh fa0, %lo(.LCPI1_0)(a0) 57; RV64IDZFH-NEXT: ret 58 ret half -0.0 59} 60