Searched refs:fs0 (Results 1 – 25 of 41) sorted by relevance
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27 ; RV32I-NOT: fsw fs0, {{[0-9]+}}(sp)28 ; RV32I-NOT: fsd fs0, {{[0-9]+}}(sp)33 ; RV64I-NOT: fsw fs0, {{[0-9]+}}(sp)34 ; RV64I-NOT: fsd fs0, {{[0-9]+}}(sp)39 ; RV32IF-NEXT: fsw fs0, {{[0-9]+}}(sp)45 ; RV64IF-NEXT: fsw fs0, {{[0-9]+}}(sp)51 ; RV32ID-NEXT: fsd fs0, {{[0-9]+}}(sp)57 ; RV64ID-NEXT: fsd fs0, {{[0-9]+}}(sp)
40 ; RV32F-NEXT: flw fs0, %lo(gf)(a1)43 ; RV32F-NEXT: fadd.s ft0, fa0, fs051 ; RV64F-NEXT: flw fs0, %lo(gf)(a1)54 ; RV64F-NEXT: fadd.s ft0, fa0, fs059 %2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1)
89 ; CHECK-NEXT: fsd fs0, 8(sp)94 ; CHECK-NEXT: fmv.s fs0, fa097 ; CHECK-NEXT: fadd.s fa0, fs0, fa0100 ; CHECK-NEXT: fld fs0, 8(sp)120 ; CHECK-NEXT: fsd fs0, 8(sp)125 ; CHECK-NEXT: fmv.s fs0, fa0128 ; CHECK-NEXT: fmul.s fa0, fs0, fa0131 ; CHECK-NEXT: fld fs0, 8(sp)
50 ; RV32F-NEXT: fld fs0, %lo(gd)(a0)52 ; RV32F-NEXT: fadd.d ft0, fa1, fs063 ; RV64F-NEXT: fld fs0, %lo(gd)(a1)66 ; RV64F-NEXT: fadd.d ft0, fa1, fs071 %2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double %a, double %1)
346 ; RV32IF-NEXT: fsw fs0, 8(sp)347 ; RV32IF-NEXT: fmv.s fs0, fa1350 ; RV32IF-NEXT: fsgnj.s fa0, fa0, fs0351 ; RV32IF-NEXT: flw fs0, 8(sp)360 ; RV32IFD-NEXT: fsd fs0, 0(sp)361 ; RV32IFD-NEXT: fmv.s fs0, fa1364 ; RV32IFD-NEXT: fsgnj.s fa0, fa0, fs0365 ; RV32IFD-NEXT: fld fs0, 0(sp)374 ; RV64IFD-NEXT: fsd fs0, 0(sp)375 ; RV64IFD-NEXT: fmv.s fs0, fa1[all …]
122 ; RV32IZFH-NEXT: fsw fs0, 8(sp)123 ; RV32IZFH-NEXT: fmv.h fs0, fa0127 ; RV32IZFH-NEXT: fadd.h fa0, ft0, fs0128 ; RV32IZFH-NEXT: flw fs0, 8(sp)137 ; RV64IZFH-NEXT: fsw fs0, 4(sp)138 ; RV64IZFH-NEXT: fmv.h fs0, fa0142 ; RV64IZFH-NEXT: fadd.h fa0, ft0, fs0143 ; RV64IZFH-NEXT: flw fs0, 4(sp)
18 ; fs0-fs11 are callee-saved for the ilp32f, ilp32d, lp64f, and lp64d ABIs.48 ; ILP32-NEXT: flw fs0, 80(a1)71 ; ILP32-NEXT: fsw fs0, 80(a1)118 ; LP64-NEXT: flw fs0, 80(a1)141 ; LP64-NEXT: fsw fs0, 80(a1)167 ; ILP32F-NEXT: fsw fs0, 44(sp)201 ; ILP32F-NEXT: flw fs0, 80(a1)224 ; ILP32F-NEXT: fsw fs0, 80(a1)256 ; ILP32F-NEXT: flw fs0, 44(sp)263 ; LP64F-NEXT: fsw fs0, 44(sp)[all …]
14 ; fs0-fs11 are callee-saved for the ilp32f, ilp32d, lp64f, and lp64d ABIs.44 ; ILP32-NEXT: fld fs0, 160(a1)67 ; ILP32-NEXT: fsd fs0, 160(a1)114 ; LP64-NEXT: fld fs0, 160(a1)137 ; LP64-NEXT: fsd fs0, 160(a1)163 ; ILP32D-NEXT: fsd fs0, 88(sp)197 ; ILP32D-NEXT: fld fs0, 160(a1)220 ; ILP32D-NEXT: fsd fs0, 160(a1)252 ; ILP32D-NEXT: fld fs0, 88(sp)259 ; LP64D-NEXT: fsd fs0, 88(sp)[all …]
41 ; CHECK-NEXT: flw fs0, 80(a0)64 ; CHECK-NEXT: fsw fs0, 0(sp)
339 ; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved.344 ; RV32IF-NEXT: fsw fs0, 12(sp)345 ; RV32IF-NEXT: fmv.s fs0, fa0347 ; RV32IF-NEXT: fcvt.w.s a0, fs0349 ; RV32IF-NEXT: flw fs0, 12(sp)356 ; RV64IF-NEXT: fsw fs0, 12(sp)357 ; RV64IF-NEXT: fmv.s fs0, fa0359 ; RV64IF-NEXT: fcvt.w.s a0, fs0361 ; RV64IF-NEXT: flw fs0, 12(sp)368 ; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved.[all …]
339 ; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved.344 ; RV32IFD-NEXT: fsd fs0, 8(sp)345 ; RV32IFD-NEXT: fmv.d fs0, fa0347 ; RV32IFD-NEXT: fcvt.w.d a0, fs0349 ; RV32IFD-NEXT: fld fs0, 8(sp)356 ; RV64IFD-NEXT: fsd fs0, 8(sp)357 ; RV64IFD-NEXT: fmv.d fs0, fa0359 ; RV64IFD-NEXT: fcvt.w.d a0, fs0361 ; RV64IFD-NEXT: fld fs0, 8(sp)368 ; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved.[all …]
124 ; RV32I-FP-SR-NEXT: fsw fs0, 12(sp)125 ; RV32I-FP-SR: flw fs0, 12(sp)132 ; RV64I-FP-SR-NEXT: fsd fs0, 8(sp)133 ; RV64I-FP-SR: fld fs0, 8(sp)
23 flw fs0, 124(s0)25 # CHECK-ALIAS: flw fs0, 124(s0)26 # CHECK-INST: c.flw fs0, 124(s0)28 fsw fs0, 124(s0)30 # CHECK-ALIAS: fsw fs0, 124(s0)31 # CHECK-INST: c.fsw fs0, 124(s0)
7 # CHECK-EXPAND: c.flw fs0, 0(s1)9 # CHECK-EXPAND: c.fsw fs0, 0(s1)11 # CHECK-EXPAND: c.flwsp fs0, 0(sp)13 # CHECK-EXPAND: c.fswsp fs0, 0(sp)
35 fld fs0, 248(s0)37 # CHECK-ALIAS: fld fs0, 248(s0)38 # CHECK-INST: c.fld fs0, 248(s0)40 fsd fs0, 248(s0)42 # CHECK-ALIAS: fsd fs0, 248(s0)43 # CHECK-INST: c.fsd fs0, 248(s0)
13 # CHECK-EXPAND: c.fsd fs0, 0(s1)15 # CHECK-EXPAND: c.fldsp fs0, 0(sp)17 # CHECK-EXPAND: c.fsdsp fs0, 0(sp)
13 # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp)17 c.fldsp fs0, 504(sp)
19 # CHECK-ASM-AND-OBJ: c.flwsp fs0, 252(sp)24 c.flwsp fs0, 252(sp)
11 c.fld fs0, -8(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 8 bytes in the ra…
11 c.flw fs0, -4(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 4 bytes in the ra…
1testfile-riscv64-dis1.o: elf64-elf_riscv 2 3Disassembly of section .text ...
55 #define fs0 $f20 macro103 #define fs0 $f24 macro
44 static unsigned ec_laplace_get_freq1(unsigned fs0, int decay) in ec_laplace_get_freq1() argument47 ft = 32768 - LAPLACE_MINP*(2*LAPLACE_NMIN) - fs0; in ec_laplace_get_freq1()
21 %fs0 = select i1 %cmp, float %arg0, float %arg127 %s0 = fadd float %fs0, %fs1