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/external/llvm/test/MC/AMDGPU/
Dflat.s23 flat_load_dword v1, v[3:4] glc
28 flat_load_dword v1, v[3:4] glc slc
33 flat_load_dword v1, v[3:4] glc tfe
38 flat_load_dword v1, v[3:4] glc slc tfe
62 flat_store_dword v[3:4], v1 glc
66 flat_store_dword v[3:4], v1 glc slc
70 flat_store_dword v[3:4], v1 glc tfe
74 flat_store_dword v[3:4], v1 glc slc tfe
100 flat_atomic_add v1 v[3:4], v5 glc slc
105 flat_atomic_add v1 v[3:4], v5 glc tfe
[all …]
Dmubuf.s29 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc
41 buffer_load_dword v1, off, s[4:7], s1 glc tfe
45 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
49 buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe
65 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc
77 buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe
81 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe
85 buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe
101 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc
113 buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe
[all …]
/external/llvm-project/llvm/test/MC/AMDGPU/
Dflat.s23 flat_load_dword v1, v[3:4] glc
28 flat_load_dword v1, v[3:4] glc slc
37 flat_store_dword v[3:4], v1 glc
41 flat_store_dword v[3:4], v1 glc slc
55 flat_atomic_add v1, v[3:4], v5 offset:0 glc slc
140 flat_atomic_swap v1, v[3:4], v5 glc
150 flat_atomic_cmpswap v1, v[3:4], v[5:6] glc
160 flat_atomic_add v1, v[3:4], v5 glc
170 flat_atomic_sub v1, v[3:4], v5 glc
180 flat_atomic_smin v1, v[3:4], v5 glc
[all …]
Dmubuf.s29 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc
41 buffer_load_dword v1, off, s[4:7], s1 glc tfe
45 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe
49 buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe
65 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc
77 buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe
81 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe
85 buffer_load_dword v1, v2, ttmp[4:7], s1 offen offset:4 glc slc tfe
101 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc
113 buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe
[all …]
Dsmem.s72 s_store_dword s1, s[2:3], 0xfc glc
82 s_store_dword s1, s[2:3], s4 glc
112 s_load_dword s1, s[2:3], 0xfc glc
117 s_load_dword s1, s[2:3], s4 glc
162 s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc
167 s_buffer_store_dwordx2 tba, s[92:95], m0 glc
226 s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc
240 s_scratch_load_dword s5, s[2:3], s0 glc
250 s_scratch_load_dwordx2 s[10:11], s[2:3], 0x1 glc
265 s_scratch_store_dword s1, s[4:5], 0x123 glc
[all …]
Dgfx1030_new.s9 global_load_dword_addtid v1, s[2:3] offset:16 glc slc dlc
12 global_store_dword_addtid v1, s[2:3] offset:16 glc slc dlc
18 global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc
21 global_atomic_csub v2, v[0:1], v2, off glc
24 global_atomic_csub v2, v0, v2, s[2:3] glc
27 global_atomic_csub v2, v0, v2, s[2:3] offset:100 glc slc
30 buffer_atomic_csub v5, off, s[8:11], s3 glc
33 buffer_atomic_csub v5, off, s[8:11], s3 offset:4095 glc
36 buffer_atomic_csub v5, off, s[8:11], -1 offset:4095 glc
39 buffer_atomic_csub v5, v0, s[8:11], s3 offen offset:4095 glc
[all …]
Dflat-gfx10.s16 flat_load_dword v1, v[3:4] offset:4 glc
19 flat_load_dword v1, v[3:4] offset:4 glc slc
22 flat_load_dword v1, v[3:4] offset:4 glc slc dlc
40 flat_atomic_cmpswap v[1:2], v[3:4] offset:2047 glc
43 flat_atomic_cmpswap v[1:2], v[3:4] glc
46 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047 glc
49 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047 glc slc
52 flat_atomic_cmpswap v0, v[1:2], v[3:4] glc
55 flat_atomic_cmpswap v0, v[1:2], v[3:4] glc slc
58 flat_atomic_cmpswap v0, v[1:2], v[3:4] glc
Dflat-gfx9.s24 flat_load_dword v1, v[3:4] offset:4 glc
28 flat_load_dword v1, v[3:4] offset:4 glc slc
56 flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 glc
59 flat_atomic_cmpswap v[1:2], v[3:4] glc
62 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
66 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc slc
70 flat_atomic_cmpswap v0, v[1:2], v[3:4] glc
74 flat_atomic_cmpswap v0, v[1:2], v[3:4] glc slc
Dmimg.s39 image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16
72 image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16
257 image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc tfe lwe da
263 image_load_pck v5, v[1:4], s[8:15] dmask:0x1 glc
291 image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm glc slc lwe da
386 image_atomic_add v4, v192, s[28:35] dmask:0x1 unorm glc
390 image_atomic_add v4, v[192:193], s[28:35] dmask:0x1 unorm glc
394 image_atomic_add v4, v[192:194], s[28:35] dmask:0x1 unorm glc
398 image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc
410 image_atomic_add v7, v3, s[0:7] dmask:0x1 glc
[all …]
Dmubuf-gfx10.s3 buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds
6 buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds dlc
9 buffer_load_sbyte v5, off, s[8:11], s3 glc slc dlc
27 buffer_atomic_fmax v0, off, s[0:3], s0 offset:4095 glc
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dglobal_atomics.ll57 ; SIVI: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}}
60 … global_atomic_add v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:16 glc{{$}}
82 …dd [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
83 ; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
86 ; GFX9: global_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}}
107 ; SIVI: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
110 ; GFX9: global_atomic_add [[RET:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] glc{{…
131 …r_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
132 ; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
135 ; GFX9: global_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}}
[all …]
Dglobal_atomics_i64.ll17 …uffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}}
20 …[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:32 glc{{$}}
42 …[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}}
43 …lat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
46 …x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}, off offset:32 glc{{$}}
66 ; CIVI: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
69 …d_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}} glc{{$}}
89 …2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
90 …lat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
93 …tomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}, off glc{{$}}
[all …]
Dllvm.amdgcn.image.atomic.dim.ll6 ; GFX6789: image_atomic_swap v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
7 ; GFX10: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
16 ; GFX6789: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 unorm glc{{$}}
17 ; GFX10: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc ;
26 ; GFX6789: image_atomic_add v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
27 ; GFX10: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
36 ; GFX6789: image_atomic_sub v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
37 ; GFX10: image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
46 ; GFX6789: image_atomic_smin v0, v1, s[0:7] dmask:0x1 unorm glc{{$}}
47 ; GFX10: image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ;
[all …]
Dllvm.amdgcn.buffer.atomic.ll6 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
9 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
11 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc
13 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
16 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc
18 ;SICI: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc
19 ;VI: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:4 glc
38 ;CHECK: buffer_atomic_swap_x2 v[3:4], off, s[0:3], 0 glc
41 ;CHECK: buffer_atomic_swap_x2 v[3:4], v1, s[0:3], 0 idxen glc
43 ;CHECK: buffer_atomic_swap_x2 v[3:4], v2, s[0:3], 0 offen glc
[all …]
Dllvm.amdgcn.struct.buffer.atomic.ll6 ;CHECK: buffer_atomic_swap v0, {{v[0-9]+}}, s[0:3], 0 idxen glc
8 ;CHECK: buffer_atomic_swap v0, {{v[0-9]+}}, s[0:3], 0 idxen glc
11 ;CHECK: buffer_atomic_swap v0, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen glc
13 ;CHECK: buffer_atomic_swap v0, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen glc
15 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen offset:42 glc
17 ;CHECK: buffer_atomic_swap v0, {{v[0-9]+}}, s[0:3], [[SOFS]] idxen offset:4 glc
20 ;CHECK: buffer_atomic_swap v0, {{v[0-9]+}}, s[0:3], 0 idxen glc
38 ;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc{{$}}
40 ;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc slc
42 ;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 idxen glc{{$}}
[all …]
Dflat_atomics.ll35 ; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
36 ; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
58 ; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
59 ; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
79 ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
98 ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
119 ; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
120 ; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
142 ; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
143 ; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
[all …]
Dllvm.amdgcn.raw.buffer.atomic.ll6 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
9 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc
11 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 offen offset:42 glc
13 ;CHECK: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:4 glc
16 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
32 ;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 offen glc{{$}}
34 ;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 offen glc slc
36 ;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 offen glc{{$}}
38 ;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 offen glc slc
40 ;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 offen glc{{$}}
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.buffer.atomic.ll5 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
8 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
10 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc
12 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
14 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc
16 ;SICI: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc
17 ;VI: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:1 glc
35 ;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc
37 ;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc
39 ;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 idxen glc
[all …]
Dglobal_atomics_i64.ll14 …uffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}}
36 …[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}}
37 …lat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
57 ; GCN: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
77 …2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
78 …lat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
98 …uffer_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}}
120 …[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}}
121 …lat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
141 ; GCN: buffer_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
[all …]
Dglobal_atomics.ll37 ; GCN: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}}
59 …dd [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
60 ; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
80 ; GCN: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
100 …r_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
101 ; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
121 ; GCN: buffer_atomic_and [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}}
143 …nd [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
144 ; VI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
164 ; GCN: buffer_atomic_and [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
[all …]
Dllvm.amdgcn.image.atomic.ll5 ;SI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00…
6 ;VI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00…
16 ;SI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00…
17 ;VI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00…
27 ;SI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x0…
28 ;VI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x0…
38 ;SI: image_atomic_cmpswap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x40,0x…
39 ;VI: image_atomic_cmpswap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x44,0x…
50 ;SI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0x00,…
51 ;VI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x00,…
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dflat_vi.txt6 # VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
9 # VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
15 # VI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x00,0x01]
54 # VI: flat_atomic_swap v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x01,0xdd,0x03,0x05,0x00,0x01]
60 # VI: flat_atomic_cmpswap v1, v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x05,0xdd,0x03,0x05,0x00,0x…
66 # VI: flat_atomic_add v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x09,0xdd,0x03,0x05,0x00,0x01]
72 # VI: flat_atomic_sub v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x0d,0xdd,0x03,0x05,0x00,0x01]
78 # VI: flat_atomic_smin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x11,0xdd,0x03,0x05,0x00,0x01]
84 # VI: flat_atomic_umin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x15,0xdd,0x03,0x05,0x00,0x01]
90 # VI: flat_atomic_smax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x19,0xdd,0x03,0x05,0x00,0x01]
[all …]
Dmubuf_vi.txt9 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x…
18 # VI: buffer_load_dword v1, off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x50,0xe0,0x00,0x01,0x…
21 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0…
30 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc ; encoding: [0x04,0x50,0x50,0xe0,0x…
39 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x50,0xe0,0x02,0x…
42 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52…
51 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x50,0xe0,0x…
60 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x50,0xe0,0x02,0x…
63 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52…
72 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x…
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dflat_vi.txt6 # VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
9 # VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
12 # VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
15 # VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
27 # VI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x00,0x01]
30 # VI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0x09,0xdd,0x03,0x05,0x80,0x01]
33 # VI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x80,0x…
78 # VI: flat_atomic_swap v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x01,0xdd,0x03,0x05,0x00,0x01]
84 # VI: flat_atomic_cmpswap v1, v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x05,0xdd,0x03,0x05,0x00,0x…
90 # VI: flat_atomic_add v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x09,0xdd,0x03,0x05,0x00,0x01]
[all …]
Dmubuf_vi.txt9 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x…
18 # VI: buffer_load_dword v1, off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x50,0xe0,0x00,0x01,0x…
21 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0…
30 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc ; encoding: [0x04,0x50,0x50,0xe0,0x…
39 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x50,0xe0,0x02,0x…
42 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x52…
51 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x50,0xe0,0x…
60 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x50,0xe0,0x02,0x…
63 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52…
72 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x…
[all …]

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