1;RUN: llc < %s -march=amdgcn -mcpu=verde -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI 3 4;CHECK-LABEL: {{^}}test1: 5;CHECK-NOT: s_waitcnt 6;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc 7;CHECK: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc 8;CHECK: s_waitcnt vmcnt(0) 9;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc 10;CHECK: s_waitcnt vmcnt(0) 11;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 offen offset:42 glc 12;CHECK-DAG: s_waitcnt vmcnt(0) 13;CHECK: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:4 glc 14;CHECK: s_waitcnt vmcnt(0) 15;CHECK: buffer_atomic_swap v0, off, s[0:3], 0{{$}} 16;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc 17define amdgpu_ps float @test1(<4 x i32> inreg %rsrc, i32 %data, i32 %voffset) { 18main_body: 19 %o1 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i32 0) 20 %o3 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %o1, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) 21 %off5 = add i32 %voffset, 42 22 %o5 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %o3, <4 x i32> %rsrc, i32 %off5, i32 0, i32 0) 23 %o6 = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %o5, <4 x i32> %rsrc, i32 4, i32 8188, i32 0) 24 %unused = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %o6, <4 x i32> %rsrc, i32 0, i32 0, i32 0) 25 %o7 = bitcast i32 %o6 to float 26 %out = call float @llvm.amdgcn.raw.buffer.atomic.swap.f32(float %o7, <4 x i32> %rsrc, i32 0, i32 0, i32 0) 27 ret float %out 28} 29 30;CHECK-LABEL: {{^}}test2: 31;CHECK-NOT: s_waitcnt 32;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 offen glc{{$}} 33;CHECK: s_waitcnt vmcnt(0) 34;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 offen glc slc 35;CHECK: s_waitcnt vmcnt(0) 36;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 offen glc{{$}} 37;CHECK: s_waitcnt vmcnt(0) 38;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 offen glc slc 39;CHECK: s_waitcnt vmcnt(0) 40;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 offen glc{{$}} 41;CHECK: s_waitcnt vmcnt(0) 42;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 offen glc slc 43;CHECK: s_waitcnt vmcnt(0) 44;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 offen glc{{$}} 45;CHECK: s_waitcnt vmcnt(0) 46;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 offen glc slc 47;CHECK: s_waitcnt vmcnt(0) 48;CHECK: buffer_atomic_xor v0, v1, s[0:3], 0 offen glc 49;CHECK: s_waitcnt vmcnt(0) 50;CHECK: buffer_atomic_inc v0, v1, s[0:3], 0 offen glc 51;CHECK: s_waitcnt vmcnt(0) 52;CHECK: buffer_atomic_dec v0, v1, s[0:3], 0 offen glc 53define amdgpu_ps float @test2(<4 x i32> inreg %rsrc, i32 %data, i32 %voffset) { 54main_body: 55 %t1 = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %data, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) 56 %t2 = call i32 @llvm.amdgcn.raw.buffer.atomic.sub.i32(i32 %t1, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 2) 57 %t3 = call i32 @llvm.amdgcn.raw.buffer.atomic.smin.i32(i32 %t2, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) 58 %t4 = call i32 @llvm.amdgcn.raw.buffer.atomic.umin.i32(i32 %t3, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 2) 59 %t5 = call i32 @llvm.amdgcn.raw.buffer.atomic.smax.i32(i32 %t4, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) 60 %t6 = call i32 @llvm.amdgcn.raw.buffer.atomic.umax.i32(i32 %t5, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 2) 61 %t7 = call i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32 %t6, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) 62 %t8 = call i32 @llvm.amdgcn.raw.buffer.atomic.or.i32(i32 %t7, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 2) 63 %t9 = call i32 @llvm.amdgcn.raw.buffer.atomic.xor.i32(i32 %t8, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) 64 %t10 = call i32 @llvm.amdgcn.raw.buffer.atomic.inc.i32(i32 %t9, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) 65 %t11 = call i32 @llvm.amdgcn.raw.buffer.atomic.dec.i32(i32 %t10, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) 66 %out = bitcast i32 %t11 to float 67 ret float %out 68} 69 70; Ideally, we would teach tablegen & friends that cmpswap only modifies the 71; first vgpr. Since we don't do that yet, the register allocator will have to 72; create copies which we don't bother to track here. 73; 74;CHECK-LABEL: {{^}}test3: 75;CHECK-NOT: s_waitcnt 76;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 0 glc 77;CHECK: s_waitcnt vmcnt(0) 78;CHECK: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc 79;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v2, s[0:3], 0 offen glc 80;CHECK: s_waitcnt vmcnt(0) 81;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v2, s[0:3], 0 offen offset:44 glc 82;CHECK-DAG: s_waitcnt vmcnt(0) 83;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[SOFS]] offset:4 glc 84define amdgpu_ps float @test3(<4 x i32> inreg %rsrc, i32 %data, i32 %cmp, i32 %vindex, i32 %voffset) { 85main_body: 86 %o1 = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %data, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i32 0) 87 %o3 = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %o1, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 0, i32 0) 88 %ofs.5 = add i32 %voffset, 44 89 %o5 = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %o3, i32 %cmp, <4 x i32> %rsrc, i32 %ofs.5, i32 0, i32 0) 90 %o6 = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %o5, i32 %cmp, <4 x i32> %rsrc, i32 4, i32 8188, i32 0) 91 92; Detecting the no-return variant doesn't work right now because of how the 93; intrinsic is replaced by an instruction that feeds into an EXTRACT_SUBREG. 94; Since there probably isn't a reasonable use-case of cmpswap that discards 95; the return value, that seems okay. 96; 97; %unused = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %o6, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i32 0) 98 %out = bitcast i32 %o6 to float 99 ret float %out 100} 101 102;CHECK-LABEL: {{^}}test4: 103;CHECK: buffer_atomic_add v0, 104define amdgpu_ps float @test4() { 105main_body: 106 %v = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 1, <4 x i32> undef, i32 4, i32 0, i32 0) 107 %v.float = bitcast i32 %v to float 108 ret float %v.float 109} 110 111declare i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32, <4 x i32>, i32, i32, i32) #0 112declare float @llvm.amdgcn.raw.buffer.atomic.swap.f32(float, <4 x i32>, i32, i32, i32) #0 113declare i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32) #0 114declare i32 @llvm.amdgcn.raw.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i32) #0 115declare i32 @llvm.amdgcn.raw.buffer.atomic.smin.i32(i32, <4 x i32>, i32, i32, i32) #0 116declare i32 @llvm.amdgcn.raw.buffer.atomic.umin.i32(i32, <4 x i32>, i32, i32, i32) #0 117declare i32 @llvm.amdgcn.raw.buffer.atomic.smax.i32(i32, <4 x i32>, i32, i32, i32) #0 118declare i32 @llvm.amdgcn.raw.buffer.atomic.umax.i32(i32, <4 x i32>, i32, i32, i32) #0 119declare i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32, <4 x i32>, i32, i32, i32) #0 120declare i32 @llvm.amdgcn.raw.buffer.atomic.or.i32(i32, <4 x i32>, i32, i32, i32) #0 121declare i32 @llvm.amdgcn.raw.buffer.atomic.xor.i32(i32, <4 x i32>, i32, i32, i32) #0 122declare i32 @llvm.amdgcn.raw.buffer.atomic.inc.i32(i32, <4 x i32>, i32, i32, i32) #0 123declare i32 @llvm.amdgcn.raw.buffer.atomic.dec.i32(i32, <4 x i32>, i32, i32, i32) #0 124declare i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32, i32, <4 x i32>, i32, i32, i32) #0 125 126attributes #0 = { nounwind } 127