| /external/arm-trusted-firmware/bl32/tsp/ |
| D | tsp_main.c | 124 read_mpidr(), in tsp_main()
152 INFO("TSP: cpu 0x%lx turned on\n", read_mpidr()); in tsp_cpu_on_main()
154 read_mpidr(), in tsp_cpu_on_main()
193 INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); in tsp_cpu_off_main()
195 read_mpidr(), in tsp_cpu_off_main()
237 read_mpidr(), in tsp_cpu_suspend_main()
275 read_mpidr(), max_off_pwrlvl); in tsp_cpu_resume_main()
277 read_mpidr(), in tsp_cpu_resume_main()
308 INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr()); in tsp_system_off_main()
309 INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(), in tsp_system_off_main()
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| D | tsp_interrupt.c | 40 read_mpidr(), elr_el3); in tsp_update_sync_sel1_intr_stats()
43 read_mpidr(), in tsp_update_sync_sel1_intr_stats()
63 read_mpidr(), tsp_stats[linear_id].preempt_intr_count); in tsp_handle_preemption()
110 read_mpidr(), id); in tsp_common_int_handler()
112 read_mpidr(), tsp_stats[linear_id].sel1_intr_count); in tsp_common_int_handler()
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| /external/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/ |
| D | plat_psci_handlers.c | 67 int cpu = read_mpidr() & MPIDR_CPU_MASK; in tegra_soc_validate_power_state()
128 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); in tegra_soc_pwr_domain_off()
151 int cpu = read_mpidr() & MPIDR_CPU_MASK; in tegra_soc_pwr_domain_suspend()
161 tegra_fc_cpu_powerdn(read_mpidr()); in tegra_soc_pwr_domain_suspend()
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| /external/arm-trusted-firmware/plat/rockchip/common/aarch64/ |
| D | platform_common.c | 78 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
85 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
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| /external/arm-trusted-firmware/services/spd/tlkd/ |
| D | tlkd_pm.c | 43 int cpu = read_mpidr() & MPIDR_CPU_MASK; in cpu_suspend_handler()
75 int cpu = read_mpidr() & MPIDR_CPU_MASK; in cpu_resume_handler()
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| /external/arm-trusted-firmware/plat/mediatek/mt8173/aarch64/ |
| D | platform_common.c | 83 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
88 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/aarch64/ |
| D | platform_common.c | 72 cci_enable_cluster_coherency(read_mpidr()); in plat_mtk_cci_enable()
77 cci_disable_cluster_coherency(read_mpidr()); in plat_mtk_cci_disable()
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| /external/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | hikey_pm.c | 39 curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); in hikey_pwr_domain_on()
55 mpidr = read_mpidr(); in hikey_pwr_domain_on_finish()
81 mpidr = read_mpidr(); in hikey_pwr_domain_off()
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| D | hikey_bl1_setup.c | 160 ep_info->args.arg0 = 0xffff & read_mpidr(); in bl1_plat_set_ep_info()
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| /external/arm-trusted-firmware/plat/renesas/common/ |
| D | bl31_plat_setup.c | 59 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
64 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
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| /external/arm-trusted-firmware/plat/allwinner/common/ |
| D | sunxi_pm.c | 101 scpi_set_css_power_state(read_mpidr(), in sunxi_pwr_domain_off()
110 sunxi_cpu_off(read_mpidr()); in sunxi_pwr_down_wfi()
139 sunxi_disable_secondary_cpus(read_mpidr()); in sunxi_system_off()
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| /external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/ |
| D | plat_psci_handlers.c | 107 int core_pos = read_mpidr() & MPIDR_CPU_MASK; in tegra_soc_get_target_pwr_state()
196 u_register_t mpidr = read_mpidr(); in tegra_soc_pwr_domain_suspend()
343 u_register_t mpidr = read_mpidr(); in tegra_soc_pwr_domain_power_down_wfi()
580 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); in tegra_soc_pwr_domain_off()
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/ |
| D | plat_pm.c | 328 uint64_t mpidr = read_mpidr(); in plat_mtk_power_domain_off()
347 uint64_t mpidr = read_mpidr(); in plat_mtk_power_domain_on_finish()
363 uint64_t mpidr = read_mpidr(); in plat_mtk_power_domain_suspend()
404 uint64_t mpidr = read_mpidr(); in plat_mtk_power_domain_suspend_finish()
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| /external/arm-trusted-firmware/plat/layerscape/board/ls1043/ |
| D | ls1043_bl1_setup.c | 50 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in bl1_early_platform_setup()
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| D | ls1043_bl31_setup.c | 52 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in bl31_early_platform_setup2()
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| /external/arm-trusted-firmware/plat/mediatek/mt8192/ |
| D | plat_topology.c | 45 if (read_mpidr() & MPIDR_MT_MASK) { in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/nvidia/tegra/drivers/flowctrl/ |
| D | flowctrl.c | 86 unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; in tegra_fc_ccplex_pgexit_lock()
178 unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; in tegra_fc_is_ccx_allowed()
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| /external/arm-trusted-firmware/plat/brcm/board/common/ |
| D | timer_sync.c | 69 cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr()); in brcm_timer_sync_init()
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| /external/arm-trusted-firmware/plat/layerscape/common/ |
| D | ls_bl2_setup.c | 85 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); in ls_bl2_handle_post_image_load()
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| /external/arm-trusted-firmware/plat/brcm/board/stingray/src/ |
| D | pm.c | 61 unsigned long cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr()); in brcm_pwr_domain_on_finish()
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| /external/arm-trusted-firmware/plat/mediatek/mt6795/ |
| D | bl31_plat_setup.c | 116 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
121 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
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| /external/arm-trusted-firmware/plat/rpi/rpi3/ |
| D | rpi3_bl2_setup.c | 131 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); in bl2_plat_handle_post_image_load()
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| /external/arm-trusted-firmware/plat/nvidia/tegra/drivers/pmc/ |
| D | pmc.c | 105 int i, cpu = read_mpidr() & MPIDR_CPU_MASK; in tegra_pmc_is_last_on_cpu()
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| /external/arm-trusted-firmware/plat/marvell/armada/common/ |
| D | marvell_bl2_setup.c | 129 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); in marvell_bl2_handle_post_image_load()
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| /external/arm-trusted-firmware/plat/arm/board/fvp/ |
| D | fvp_gicv3.c | 169 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); in plat_arm_gic_pcpu_init()
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