| /external/ethtool/ |
| D | et131x.c | 9 u32 *reg = (u32 *)regs->data; in et131x_dump_regs() local
15 fprintf(stdout, "0x0, Basic Control Reg = 0x%04X\n", *reg++); in et131x_dump_regs()
16 fprintf(stdout, "0x1, Basic Status Reg = 0x%04X\n", *reg++); in et131x_dump_regs()
17 fprintf(stdout, "0x2, PHY identifier 1 = 0x%04X\n", *reg++); in et131x_dump_regs()
18 fprintf(stdout, "0x3, PHY identifier 2 = 0x%04X\n", *reg++); in et131x_dump_regs()
19 fprintf(stdout, "0x4, Auto Neg Advertisement = 0x%04X\n", *reg++); in et131x_dump_regs()
20 fprintf(stdout, "0x5, Auto Neg L Partner Ability = 0x%04X\n", *reg++); in et131x_dump_regs()
21 fprintf(stdout, "0x6, Auto Neg Expansion = 0x%04X\n", *reg++); in et131x_dump_regs()
22 fprintf(stdout, "0x7, Reserved = 0x%04X\n", *reg++); in et131x_dump_regs()
23 fprintf(stdout, "0x8, Reserved = 0x%04X\n", *reg++); in et131x_dump_regs()
[all …]
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| D | e1000.c | 374 u32 reg; in e1000_dump_regs() local
388 reg = regs_buff[0]; in e1000_dump_regs()
398 reg, in e1000_dump_regs()
399 reg & E1000_CTRL_BEM ? "big" : "little", in e1000_dump_regs()
400 reg & E1000_CTRL_LRST ? "reset" : "normal", in e1000_dump_regs()
401 reg & E1000_CTRL_SLU ? "1" : "0", in e1000_dump_regs()
402 reg & E1000_CTRL_ILOS ? "yes" : "no", in e1000_dump_regs()
403 reg & E1000_CTRL_RFCE ? "enabled" : "disabled", in e1000_dump_regs()
404 reg & E1000_CTRL_TFCE ? "enabled" : "disabled", in e1000_dump_regs()
405 reg & E1000_CTRL_VME ? "enabled" : "disabled"); in e1000_dump_regs()
[all …]
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| D | amd8111e.c | 160 u32 reg; in amd8111e_dump_regs() local
166 reg = reg_buff[0]; in amd8111e_dump_regs()
168 "0x00100: Transmit descriptor base address register %08X\n",reg); in amd8111e_dump_regs()
171 reg = reg_buff[1]; in amd8111e_dump_regs()
173 "0x00140: Transmit descriptor length register 0x%08X\n",reg); in amd8111e_dump_regs()
176 reg = reg_buff[2]; in amd8111e_dump_regs()
178 "0x00120: Receive descriptor base address register %08X\n",reg); in amd8111e_dump_regs()
181 reg = reg_buff[3]; in amd8111e_dump_regs()
183 "0x00150: Receive descriptor length register 0x%08X\n",reg); in amd8111e_dump_regs()
192 reg = reg_buff[4]; in amd8111e_dump_regs()
[all …]
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| D | dsa.c | 33 static void dsa_mv88e6161(int reg, u16 val) in dsa_mv88e6161() argument
35 switch (reg) { in dsa_mv88e6161()
37 REG(reg, "Port Status", val); in dsa_mv88e6161()
56 REG(reg, "PCS Control", val); in dsa_mv88e6161()
70 REG(reg, "Jamming Control", val); in dsa_mv88e6161()
73 REG(reg, "Switch Identifier", val); in dsa_mv88e6161()
76 REG(reg, "Port Control", val); in dsa_mv88e6161()
113 REG(reg, "Port Control 1", val); in dsa_mv88e6161()
120 REG(reg, "Port Base VLAN Map (Header)", val); in dsa_mv88e6161()
125 REG(reg, "Default VLAN ID & Priority", val); in dsa_mv88e6161()
[all …]
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| D | ixgb.c | 46 u32 reg; in ixgb_dump_regs() local
54 reg = regs_buff[0]; in ixgb_dump_regs()
59 reg, in ixgb_dump_regs()
60 reg & IXGB_CTRL0_LRST ? "reset" : "normal", in ixgb_dump_regs()
61 reg & IXGB_CTRL0_VME ? "enabled" : "disabled"); in ixgb_dump_regs()
64 reg = regs_buff[2]; in ixgb_dump_regs()
71 reg, in ixgb_dump_regs()
72 (reg & IXGB_STATUS_LU) ? "link config" : "no link config", in ixgb_dump_regs()
73 (reg & IXGB_STATUS_PCIX_MODE) ? "PCI-X" : "PCI", in ixgb_dump_regs()
74 ((reg & IXGB_STATUS_PCIX_SPD_133) ? "133MHz" : in ixgb_dump_regs()
[all …]
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| /external/llvm-project/llvm/test/CodeGen/MSP430/ |
| D | BranchSelector.ll | 5 @reg = common global i16 0, align 2
12 store volatile i16 11, i16* @reg, align 2
13 store volatile i16 13, i16* @reg, align 2
14 store volatile i16 17, i16* @reg, align 2
15 store volatile i16 11, i16* @reg, align 2
16 store volatile i16 13, i16* @reg, align 2
17 store volatile i16 17, i16* @reg, align 2
18 store volatile i16 11, i16* @reg, align 2
19 store volatile i16 13, i16* @reg, align 2
20 store volatile i16 17, i16* @reg, align 2
[all …]
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| /external/linux-kselftest/tools/testing/selftests/powerpc/include/ |
| D | vmx_asm.h | 9 #define PUSH_VMX(pos,reg) \ argument
10 li reg,pos; \
11 stvx v20,reg,%r1; \
12 addi reg,reg,16; \
13 stvx v21,reg,%r1; \
14 addi reg,reg,16; \
15 stvx v22,reg,%r1; \
16 addi reg,reg,16; \
17 stvx v23,reg,%r1; \
18 addi reg,reg,16; \
[all …]
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| /external/gemmlowp/internal/ |
| D | simd_wrappers_neon.h | 162 result.buf.reg[i] = vld1q_s16(src + 8 * i);
173 result.buf.reg[i] = vld1_u8(src + 8 * i);
184 result.buf.reg[i] = vld1_s8(src + 8 * i);
195 result.buf.reg[i] = vld1q_s32(src + 4 * i);
207 result.buf.reg[0] = ShiftLeft(lhs.buf.reg[0], Dup<Int32x4>(rhs.buf.reg[0]));
218 result.buf.reg[0] = ShiftLeft(lhs.buf.reg[0], Dup<Int32x4>(rhs.buf.reg[0]));
229 result.buf.reg[0] = ShiftLeft(lhs.buf.reg[0], rhs.buf.reg[0]);
240 result.buf.reg[0] = ShiftLeft(lhs.buf.reg[0], rhs.buf.reg[0]);
251 result.buf.reg[0] = ShiftLeft(lhs.buf.reg[0], DupLane<0>(rhs.buf.reg[0]));
252 result.buf.reg[1] = ShiftLeft(lhs.buf.reg[1], DupLane<1>(rhs.buf.reg[0]));
[all …]
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| D | simd_wrappers_common_neon_sse.h | 32 result.buf.reg[i] = LoadInt32x4(src.data(row, col + i));
46 result.buf.reg[2 * i + 0] = LoadInt32x4(src.data(row + 0, col + i));
47 result.buf.reg[2 * i + 1] = LoadInt32x4(src.data(row + 4, col + i));
64 result.buf.reg[0] = LoadInt32x4(buf);
80 result.buf.reg[0] = LoadInt32x4(buf);
81 result.buf.reg[1] = LoadInt32x4(buf + 4);
92 result.buf.reg[0] = LoadInt32x4(src.data(pos));
103 result.buf.reg[0] = LoadInt32x4(src(0));
120 result.buf.reg[0] = LoadInt32x4(src.data(pos));
137 result.buf.reg[0] = LoadInt32x4(src.data(pos));
[all …]
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| D | output_sse.h | 38 __m128i res_16 = _mm_packs_epi32(input.reg[0], input.reg[0]);
40 output.reg[0] = _mm_cvtsi128_si32(res_8);
57 __m128i res_16 = _mm_packs_epi32(input.reg[0], input.reg[1]);
59 output.reg[0] = _mm_extract_epi32(res_8, 0);
60 output.reg[1] = _mm_extract_epi32(res_8, 1);
77 __m128i res_16_0 = _mm_packs_epi32(input.reg[0], input.reg[1]);
78 __m128i res_16_1 = _mm_packs_epi32(input.reg[2], input.reg[3]);
79 output.reg[0] = _mm_packus_epi16(res_16_0, res_16_1);
96 __m128i res_16_0 = _mm_packs_epi32(input.reg[0], input.reg[1]);
97 __m128i res_16_1 = _mm_packs_epi32(input.reg[2], input.reg[3]);
[all …]
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| D | output_neon.h | 38 int16x4_t res_16 = vqmovn_s32(input.reg[0]);
40 output.reg[0] = vget_lane_u32(vreinterpret_u32_u8(res_8), 0);
58 vcombine_s16(vqmovn_s32(input.reg[0]), vqmovn_s32(input.reg[1]));
59 output.reg[0] = vqmovun_s16(res_16);
77 vcombine_s16(vqmovn_s32(input.reg[0]), vqmovn_s32(input.reg[1]));
79 vcombine_s16(vqmovn_s32(input.reg[2]), vqmovn_s32(input.reg[3]));
80 output.reg[0] = vqmovun_s16(res_16_0);
81 output.reg[1] = vqmovun_s16(res_16_1);
100 res_16[i] = vcombine_s16(vqmovn_s32(input.reg[2 * i]),
101 vqmovn_s32(input.reg[2 * i + 1]));
[all …]
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| D | output_msa.h | 40 v4i32 tmp = __builtin_msa_sat_s_w(input.reg[0], 8);
50 output.reg[0] = __builtin_msa_copy_s_w(tmp, 0);
69 v4i32 tmp_lo = __builtin_msa_sat_s_w(input.reg[0], 8);
70 v4i32 tmp_hi = __builtin_msa_sat_s_w(input.reg[1], 8);
82 output.reg[0] = __builtin_msa_copy_s_w(tmp_lo, 0);
83 output.reg[1] = __builtin_msa_copy_s_w(tmp_lo, 1);
119 GEMMLOWP_MIPS_SAT_U8_16(output.reg[0], input.reg[0], input.reg[1],
120 input.reg[2], input.reg[3]);
137 GEMMLOWP_MIPS_SAT_U8_16(output.reg[0], input.reg[0], input.reg[1],
138 input.reg[2], input.reg[3]);
[all …]
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| /external/igt-gpu-tools/assembler/ |
| D | gen8_instruction.c | 34 gen8_set_dst(struct gen8_instruction *inst, struct brw_reg reg) in gen8_set_dst() argument
37 if (reg.file == BRW_MESSAGE_REGISTER_FILE) { in gen8_set_dst()
38 reg.file = BRW_GENERAL_REGISTER_FILE; in gen8_set_dst()
39 reg.nr += GEN7_MRF_HACK_START; in gen8_set_dst()
42 assert(reg.file != BRW_MESSAGE_REGISTER_FILE); in gen8_set_dst()
44 if (reg.file == BRW_GENERAL_REGISTER_FILE) in gen8_set_dst()
45 assert(reg.nr < BRW_MAX_GRF); in gen8_set_dst()
47 gen8_set_dst_reg_file(inst, reg.file); in gen8_set_dst()
48 gen8_set_dst_reg_type(inst, reg.type); in gen8_set_dst()
50 if (reg.address_mode == BRW_ADDRESS_DIRECT) { in gen8_set_dst()
[all …]
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| D | brw_reg.h | 190 struct brw_reg reg; in brw_reg() local
198 reg.type = type; in brw_reg()
199 reg.file = file; in brw_reg()
200 reg.nr = nr; in brw_reg()
201 reg.subnr = subnr * type_sz(type); in brw_reg()
202 reg.negate = 0; in brw_reg()
203 reg.abs = 0; in brw_reg()
204 reg.vstride = vstride; in brw_reg()
205 reg.width = width; in brw_reg()
206 reg.hstride = hstride; in brw_reg()
[all …]
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| /external/igt-gpu-tools/tools/ |
| D | intel_error_decode.c | 63 print_head(unsigned int reg) in print_head() argument
65 printf(" head = 0x%08x, wraps = %d\n", reg & (0x7ffff<<2), reg >> 21); in print_head()
66 return reg & (0x7ffff<<2); in print_head()
70 print_ctl(unsigned int reg) in print_ctl() argument
72 uint32_t ring_length = (((reg & (0x1ff << 12)) >> 12) + 1) * 4096; in print_ctl()
74 #define BIT_STR(reg, x, on, off) ((1 << (x)) & reg) ? on : off in print_ctl() argument
77 BIT_STR(reg, 0, ", enabled", ", disabled"), in print_ctl()
78 BIT_STR(reg, 10, ", semaphore wait ", ""), in print_ctl()
79 BIT_STR(reg, 11, ", rb wait ", "") in print_ctl()
86 print_acthd(unsigned int reg, unsigned int ring_length) in print_acthd() argument
[all …]
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | irtranslator-amdgpu_kernel-system-sgprs.ll | 5 ; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
6 ; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
7 ; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
8 ; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
17 ; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
18 ; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
19 ; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
20 ; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
30 ; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
31 ; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
[all …]
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_build_pm4.h | 42 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq() argument
44 SI_CHECK_SHADOWED_REGS(reg, num); in radeon_set_config_reg_seq()
45 assert(reg < SI_CONTEXT_REG_OFFSET); in radeon_set_config_reg_seq()
48 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
51 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() argument
53 radeon_set_config_reg_seq(cs, reg, 1); in radeon_set_config_reg()
57 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq() argument
59 SI_CHECK_SHADOWED_REGS(reg, num); in radeon_set_context_reg_seq()
60 assert(reg >= SI_CONTEXT_REG_OFFSET); in radeon_set_context_reg_seq()
63 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
[all …]
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi_private.cpp | 54 st_src_reg *reg = ralloc(input, st_src_reg); in dup_reladdr() local
55 if (!reg) { in dup_reladdr()
60 *reg = *input; in dup_reladdr()
61 return reg; in dup_reladdr()
141 st_src_reg::st_src_reg(const st_src_reg ®) in st_src_reg() argument
143 *this = reg; in st_src_reg()
146 void st_src_reg::operator=(const st_src_reg ®) in operator =() argument
148 this->type = reg.type; in operator =()
149 this->file = reg.file; in operator =()
150 this->index = reg.index; in operator =()
[all …]
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| /external/arm-trusted-firmware/drivers/renesas/rcar/qos/ |
| D | qos_init.c | 61 #define PRR_PRODUCT_ERR(reg) \ argument
64 "initialize not supported.\n", reg); \
68 #define PRR_CUT_ERR(reg) \ argument
71 "initialize not supported.\n", reg); \
77 uint32_t reg; in rcar_qos_init() local
90 reg = mmio_read_32(PRR); in rcar_qos_init()
92 switch (reg & PRR_PRODUCT_MASK) { in rcar_qos_init()
95 switch (reg & PRR_CUT_MASK) { in rcar_qos_init()
111 switch (reg & PRR_CUT_MASK) { in rcar_qos_init()
118 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
[all …]
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| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_sanity.c | 66 scan_register_key(const scan_register *reg) in scan_register_key() argument
68 unsigned key = reg->file; in scan_register_key()
69 key |= (reg->indices[0] << 4); in scan_register_key()
70 key |= (reg->indices[1] << 18); in scan_register_key()
76 fill_scan_register1d(scan_register *reg, in fill_scan_register1d() argument
79 reg->file = file; in fill_scan_register1d()
80 reg->dimensions = 1; in fill_scan_register1d()
81 reg->indices[0] = index; in fill_scan_register1d()
82 reg->indices[1] = 0; in fill_scan_register1d()
86 fill_scan_register2d(scan_register *reg, in fill_scan_register2d() argument
[all …]
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| /external/arm-trusted-firmware/drivers/renesas/rcar/pfc/ |
| D | pfc_init.c | 40 #define PRR_PRODUCT_ERR(reg) \ argument
43 reg); \
47 #define PRR_CUT_ERR(reg) \ argument
50 reg); \
56 uint32_t reg; in rcar_pfc_init() local
58 reg = mmio_read_32(RCAR_PRR); in rcar_pfc_init()
60 switch (reg & PRR_PRODUCT_MASK) { in rcar_pfc_init()
62 switch (reg & PRR_CUT_MASK) { in rcar_pfc_init()
84 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
89 switch (reg & PRR_PRODUCT_MASK) { in rcar_pfc_init()
[all …]
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_clip_line.c | 45 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_line_alloc_regs()
48 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
60 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
64 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_line_alloc_regs()
65 c->reg.t0 = brw_vec1_grf(i, 1); in brw_clip_line_alloc_regs()
66 c->reg.t1 = brw_vec1_grf(i, 2); in brw_clip_line_alloc_regs()
67 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_line_alloc_regs()
68 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_line_alloc_regs()
71 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_line_alloc_regs()
72 c->reg.dp1 = brw_vec1_grf(i, 4); in brw_clip_line_alloc_regs()
[all …]
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| D | brw_reg.h | 415 struct brw_reg reg; in brw_reg() local
425 reg.type = type; in brw_reg()
426 reg.file = file; in brw_reg()
427 reg.negate = negate; in brw_reg()
428 reg.abs = abs; in brw_reg()
429 reg.address_mode = BRW_ADDRESS_DIRECT; in brw_reg()
430 reg.pad0 = 0; in brw_reg()
431 reg.subnr = subnr * type_sz(type); in brw_reg()
432 reg.nr = nr; in brw_reg()
440 reg.swizzle = swizzle; in brw_reg()
[all …]
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_sanity.c | 67 scan_register_key(const scan_register *reg) in scan_register_key() argument
69 unsigned key = reg->file; in scan_register_key()
70 key |= (reg->indices[0] << 4); in scan_register_key()
71 key |= (reg->indices[1] << 18); in scan_register_key()
77 fill_scan_register1d(scan_register *reg, in fill_scan_register1d() argument
80 reg->file = file; in fill_scan_register1d()
81 reg->dimensions = 1; in fill_scan_register1d()
82 reg->indices[0] = index; in fill_scan_register1d()
83 reg->indices[1] = 0; in fill_scan_register1d()
87 fill_scan_register2d(scan_register *reg, in fill_scan_register2d() argument
[all …]
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_cs.h | 43 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq() argument
45 assert(reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END); in radeon_set_config_reg_seq()
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
52 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() argument
54 radeon_set_config_reg_seq(cs, reg, 1); in radeon_set_config_reg()
58 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq() argument
60 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END); in radeon_set_context_reg_seq()
64 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
67 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg() argument
69 radeon_set_context_reg_seq(cs, reg, 1); in radeon_set_context_reg()
[all …]
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