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Searched refs:s_brev_b32 (Results 1 – 25 of 42) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dbitreverse.ll17 ; SI: s_brev_b32
35 ; SI: s_brev_b32 [[SRESULT:s[0-9]+]], [[VAL]]
58 ; SI: s_brev_b32
59 ; SI: s_brev_b32
107 ; SI: s_brev_b32
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfcopysign.f16.ll17 ; SI: s_brev_b32 s[[CONST:[0-9]+]], -2
43 ; GCN-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
67 ; GCN-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
92 ; GCN-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
118 ; GCN-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
144 ; SI-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
172 ; SI-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
200 ; SI-DAG: s_brev_b32 s[[CONST:[0-9]+]], -2
Dllvm.round.f64.ll31 ; SI-NEXT: s_brev_b32 s0, -2
47 ; CI-NEXT: s_brev_b32 s8, -2
83 ; SI-NEXT: s_brev_b32 s6, -2
120 ; CI-NEXT: s_brev_b32 s0, -2
155 ; SI-NEXT: s_brev_b32 s15, 1
173 ; SI-NEXT: s_brev_b32 s10, -2
209 ; CI-NEXT: s_brev_b32 s6, -2
250 ; SI-NEXT: s_brev_b32 s20, 1
268 ; SI-NEXT: s_brev_b32 s16, -2
350 ; CI-NEXT: s_brev_b32 s12, -2
[all …]
Dbitreverse-inline-immediates.ll182 ; GCN: s_brev_b32 s{{[0-9]+}}, 1{{$}}
189 ; GCN: s_brev_b32 s{{[0-9]+}}, 64{{$}}
203 ; GCN: s_brev_b32 s{{[0-9]+}}, -16{{$}}
Dfcopysign.f64.ll15 ; GCN-DAG: s_brev_b32 [[SCONST:s[0-9]+]], -2
30 ; GCN-DAG: s_brev_b32 [[SCONST:s[0-9]+]], -2{{$}}
Dfneg-fabs.ll87 ; SI: s_brev_b32 [[SIGNBITK:s[0-9]+]], 1{{$}}
98 ; SI: s_brev_b32 [[SIGNBITK:s[0-9]+]], 1{{$}}
Dfcopysign.f32.ll16 ; GCN-DAG: s_brev_b32 [[SCONST:s[0-9]+]], -2
Dbitreverse.ll26 ; SI-NEXT: s_brev_b32 s0, s0
39 ; FLAT-NEXT: s_brev_b32 s0, s0
95 ; SI-NEXT: s_brev_b32 s0, s0
107 ; FLAT-NEXT: s_brev_b32 s0, s0
166 ; SI-NEXT: s_brev_b32 s1, s1
167 ; SI-NEXT: s_brev_b32 s0, s0
180 ; FLAT-NEXT: s_brev_b32 s1, s1
181 ; FLAT-NEXT: s_brev_b32 s0, s0
Dfneg.ll21 ; GCN: s_brev_b32 [[SIGNBIT:s[0-9]+]], 1
Dllvm.amdgcn.s.buffer.load.ll279 ; SI: s_brev_b32 [[K:s[0-9]+]], 1{{$}}
284 ; VI: s_brev_b32 [[K:s[0-9]+]], 1{{$}}
305 ; SI: s_brev_b32 [[K:s[0-9]+]], 4{{$}}
310 ; VI: s_brev_b32 [[K:s[0-9]+]], 4{{$}}
Dllvm.round.ll8 ; GCN-DAG: s_brev_b32 [[K:s[0-9]+]], -2{{$}}
Dsi-annotate-cf.ll170 ; SI-NEXT: s_brev_b32 s9, 44
242 ; FLAT-NEXT: s_brev_b32 s9, 44
Dfpow.ll444 ; GFX6-NEXT: s_brev_b32 s4, -2
455 ; GFX8-NEXT: s_brev_b32 s4, -2
466 ; GFX9-NEXT: s_brev_b32 s4, -2
Dknown-never-snan.ll70 ; GCN-NEXT: s_brev_b32 s4, -2
458 ; GCN-NEXT: s_brev_b32 s4, -2
Durem64.ll544 ; GCN-NEXT: s_brev_b32 s0, -2
586 ; GCN-IR-NEXT: s_brev_b32 s0, -2
694 ; GCN-NEXT: s_brev_b32 s0, -2
736 ; GCN-IR-NEXT: s_brev_b32 s0, -2
Dshrink-add-sub-constant.ll1277 ; GFX9-NEXT: s_brev_b32 s2, 35
1345 ; GFX9-NEXT: s_brev_b32 s2, 34
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dshl-ext-reduce.ll278 ; GCN-NEXT: s_brev_b32 s2, -4
297 ; GFX7-NEXT: s_brev_b32 s4, -4
309 ; GFX8-NEXT: s_brev_b32 s4, -4
321 ; GFX9-NEXT: s_brev_b32 s4, -4
338 ; GCN-NEXT: s_brev_b32 s2, -8
357 ; GFX7-NEXT: s_brev_b32 s4, -8
369 ; GFX8-NEXT: s_brev_b32 s4, -8
381 ; GFX9-NEXT: s_brev_b32 s4, -8
Dssubsat.ll257 ; GFX6-NEXT: s_brev_b32 s4, -2
262 ; GFX6-NEXT: s_brev_b32 s5, 1
367 ; GFX6-NEXT: s_brev_b32 s4, -2
371 ; GFX6-NEXT: s_brev_b32 s5, 1
517 ; GFX6-NEXT: s_brev_b32 s4, -2
524 ; GFX6-NEXT: s_brev_b32 s5, 1
723 ; GFX6-NEXT: s_brev_b32 s8, -2
727 ; GFX6-NEXT: s_brev_b32 s9, 1
1274 ; GFX6-NEXT: s_brev_b32 s4, -2
1277 ; GFX6-NEXT: s_brev_b32 s5, 1
[all …]
Dsaddsat.ll257 ; GFX6-NEXT: s_brev_b32 s5, 1
262 ; GFX6-NEXT: s_brev_b32 s4, -2
367 ; GFX6-NEXT: s_brev_b32 s4, -2
371 ; GFX6-NEXT: s_brev_b32 s5, 1
517 ; GFX6-NEXT: s_brev_b32 s5, 1
524 ; GFX6-NEXT: s_brev_b32 s4, -2
723 ; GFX6-NEXT: s_brev_b32 s8, -2
727 ; GFX6-NEXT: s_brev_b32 s9, 1
1288 ; GFX6-NEXT: s_brev_b32 s5, 1
1291 ; GFX6-NEXT: s_brev_b32 s4, -2
[all …]
Droundeven.ll506 ; GFX6-NEXT: s_brev_b32 s6, 1
/external/llvm/test/MC/AMDGPU/
Dsop1.s83 s_brev_b32 s1, s2 label
/external/llvm-project/llvm/test/MC/AMDGPU/
Dsop1.s111 s_brev_b32 s1, s2 label
Dgfx7_asm_all.s11106 s_brev_b32 s5, s1 label
11109 s_brev_b32 s103, s1 label
11112 s_brev_b32 flat_scratch_lo, s1 label
11115 s_brev_b32 flat_scratch_hi, s1 label
11118 s_brev_b32 vcc_lo, s1 label
11121 s_brev_b32 vcc_hi, s1 label
11124 s_brev_b32 tba_lo, s1 label
11127 s_brev_b32 tba_hi, s1 label
11130 s_brev_b32 tma_lo, s1 label
11133 s_brev_b32 tma_hi, s1 label
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt54 # VI: s_brev_b32 s1, s2 ; encoding: [0x02,0x08,0x81,0xbe]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt63 # VI: s_brev_b32 s1, s2 ; encoding: [0x02,0x08,0x81,0xbe]

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