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Searched refs:setcc (Results 1 – 25 of 135) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
D	v_cndmask.ll	`20 %setcc = icmp ne i32 %c, 0 21 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f 41 %setcc = icmp ne i32 %c, 0 42 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f 63 %setcc = fcmp one float %x, 0.0 64 %select = select i1 %setcc, float 1.0, float %z 80 %setcc = fcmp one float %x, 0.0 81 %select = select i1 %setcc, float 1.0, float %x 97 %setcc = fcmp one float %x, 0.0 98 %select = select i1 %setcc, float 0.0, float %z [all …]`
D	sub-zext-cc-zext-cc.ll	`15 ; sub zext (setcc), x => addcarry 0, x, setcc 16 ; sub sext (setcc), x => subcarry 0, x, setcc`
D	llvm.amdgcn.is.shared.ll	`22 ; FIXME: setcc (zero_extend (setcc)), 1) not folded out, resulting in`
D	llvm.amdgcn.is.private.ll	`21 ; FIXME: setcc (zero_extend (setcc)), 1) not folded out, resulting in`
/external/llvm-project/llvm/test/CodeGen/SystemZ/
D	sext-zext.ll	`16 ;; fold (sext (not (setcc a, b, cc))) -> (sext (setcc a, b, !cc)) 31 ;; TODO: fold (add (zext (setcc a, b, cc)), -1) -> (sext (setcc a, b, !cc))`
/external/llvm/test/CodeGen/AMDGPU/
D	v_cndmask.ll	`15 %setcc = icmp ne i32 %c, 0 16 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f 32 %setcc = icmp ne i32 %c, 0 33 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f`
/external/llvm-project/llvm/test/CodeGen/PowerPC/
D	ppc32-i64-to-float-conv.ll	7 ; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be 8 ; generated. And this testcase verifies that the operand expansion of `setcc` 24 ; CHECK-NOT: Unexpected setcc expansion!
D	add_cmp.ll	`15 ; CHECK: {{t[0-9]+}}: i1 = setcc [[REG2]], Constant:i32<100>, setugt:ch 28 ; CHECK: {{t[0-9]+}}: i1 = setcc [[REG2]], Constant:i32<30>, setgt:ch 41 ; CHECK: {{t[0-9]+}}: i1 = setcc [[REG2]], Constant:i32<100>, setugt:ch 54 ; CHECK: {{t[0-9]+}}: i1 = setcc [[REG2]], Constant:i16<-32767>, setgt:ch`
D	ppc64-P9-setb.ll	9 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt 35 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt 61 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt 87 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt 113 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt 143 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt 173 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt 203 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt 233 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setgt 259 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setlt [all …]
/external/llvm-project/llvm/test/TableGen/
D	GlobalISelEmitter-setcc.td	`12 [(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, SETOEQ)))]>; 19 [(set GPR32:$dst, (i32 (setcc i32:$src0, i32:$src1, SETEQ)))]>; 24 [(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, i32)))]>;`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
D	PPCInstrQPX.td	`448 (setcc v4f64:$FRA, v4f64:$FRB, SETUO))]>; 453 (setcc v4f32:$FRA, v4f32:$FRB, SETUO))]>; 459 (setcc v4f64:$FRA, v4f64:$FRB, SETOLT))]>; 464 (setcc v4f32:$FRA, v4f32:$FRB, SETOLT))]>; 470 (setcc v4f64:$FRA, v4f64:$FRB, SETOGT))]>; 475 (setcc v4f32:$FRA, v4f32:$FRB, SETOGT))]>; 481 (setcc v4f64:$FRA, v4f64:$FRB, SETOEQ))]>; 486 (setcc v4f32:$FRA, v4f32:$FRB, SETOEQ))]>; 989 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOGE), 992 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOLE), [all …]`
D	PPCInstrInfo.td	3364 // match setcc on i1 variables. 3382 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3384 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3403 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3405 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3408 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3422 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3424 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3438 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3440 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), [all …]
/external/llvm/lib/Target/PowerPC/
D	PPCInstrQPX.td	`451 (setcc v4f64:$FRA, v4f64:$FRB, SETUO))]>; 456 (setcc v4f32:$FRA, v4f32:$FRB, SETUO))]>; 462 (setcc v4f64:$FRA, v4f64:$FRB, SETOLT))]>; 467 (setcc v4f32:$FRA, v4f32:$FRB, SETOLT))]>; 473 (setcc v4f64:$FRA, v4f64:$FRB, SETOGT))]>; 478 (setcc v4f32:$FRA, v4f32:$FRB, SETOGT))]>; 484 (setcc v4f64:$FRA, v4f64:$FRB, SETOEQ))]>; 489 (setcc v4f32:$FRA, v4f32:$FRB, SETOEQ))]>; 992 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOGE), 995 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOLE), [all …]`
D	PPCInstrInfo.td	2930 // match setcc on i1 variables. 2948 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 2950 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 2969 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 2971 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 2974 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 2988 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 2990 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3004 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3006 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), [all …]
/external/llvm/lib/Target/WebAssembly/
D	WebAssemblyInstrFormats.td	`66 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))], 69 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))], 74 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))], 77 [(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))],`
/external/llvm/include/llvm/Target/
D	TargetSelectionDAG.td	`164 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 466 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 971 // setcc convenience fragments. 973 (setcc node:$lhs, node:$rhs, SETOEQ)>; 975 (setcc node:$lhs, node:$rhs, SETOGT)>; 977 (setcc node:$lhs, node:$rhs, SETOGE)>; 979 (setcc node:$lhs, node:$rhs, SETOLT)>; 981 (setcc node:$lhs, node:$rhs, SETOLE)>; 983 (setcc node:$lhs, node:$rhs, SETONE)>; 985 (setcc node:$lhs, node:$rhs, SETO)>; [all …]`
/external/llvm-project/llvm/test/CodeGen/X86/
D	fmf-propagation.ll	`32 ; CHECK: t13: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, … 41 ; CHECK: t14: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, …`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
D	WebAssemblyInstrInteger.td	`38 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))], 42 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))], 90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))], 93 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],`
/external/llvm-project/llvm/lib/Target/WebAssembly/
D	WebAssemblyInstrInteger.td	`38 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))], 42 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))], 90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))], 93 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],`
/external/llvm-project/llvm/lib/Target/PowerPC/
D	PPCInstrInfo.td	3588 // match setcc on i1 variables. 3606 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3608 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3627 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3629 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3632 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3646 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3648 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3662 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3664 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), [all …]
/external/llvm-project/llvm/include/llvm/Target/
D	TargetSelectionDAG.td	`176 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 563 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 1280 // setcc convenience fragments. 1282 (setcc node:$lhs, node:$rhs, SETOEQ)>; 1284 (setcc node:$lhs, node:$rhs, SETOGT)>; 1286 (setcc node:$lhs, node:$rhs, SETOGE)>; 1288 (setcc node:$lhs, node:$rhs, SETOLT)>; 1290 (setcc node:$lhs, node:$rhs, SETOLE)>; 1292 (setcc node:$lhs, node:$rhs, SETONE)>; 1294 (setcc node:$lhs, node:$rhs, SETO)>; [all …]`
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
D	TargetSelectionDAG.td	`176 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 554 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 1273 // setcc convenience fragments. 1275 (setcc node:$lhs, node:$rhs, SETOEQ)>; 1277 (setcc node:$lhs, node:$rhs, SETOGT)>; 1279 (setcc node:$lhs, node:$rhs, SETOGE)>; 1281 (setcc node:$lhs, node:$rhs, SETOLT)>; 1283 (setcc node:$lhs, node:$rhs, SETOLE)>; 1285 (setcc node:$lhs, node:$rhs, SETONE)>; 1287 (setcc node:$lhs, node:$rhs, SETO)>; [all …]`
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
D	PPCGenDAGISel.inc	3552 …// Src: (anyext:{ :[i32] } (setcc:{ :[i1] } (and:{ :[i32] } i32:{ :[i32] }:$s1, (shl:{ :[i32]… 3567 …// Src: (anyext:{ :[i64] } (setcc:{ :[i1] } (and:{ :[i64] } i64:{ :[i64] }:$s1, (shl:{ :[i64]… 3591 …// Src: (anyext:{ :[i32] } (setcc:{ :[i1] } (and:{ :[i32] } (shl:{ :[i32] } 1:{ :[i32] }, i32… 3606 …// Src: (anyext:{ :[i64] } (setcc:{ :[i1] } (and:{ :[i64] } (shl:{ :[i64] } 1:{ :[i64] }, i32… 3633 …// Src: (anyext:{ :[i32] } (setcc:{ :[i1] } (and:{ :[i64] } i64:{ :[i64] }:$s1, (shl:{ :[i64]… 3648 …// Src: (anyext:{ :[i64] } (setcc:{ :[i1] } (and:{ :[i64] } i64:{ :[i64] }:$s1, (shl:{ :[i64]… 3666 …// Src: (anyext:{ :[i32] } (setcc:{ :[i1] } (and:{ :[i32] } i32:{ :[i32] }:$s1, (shl:{ :[i32]… 3693 …// Src: (anyext:{ :[i32] } (setcc:{ :[i1] } (and:{ :[i64] } (shl:{ :[i64] } 1:{ :[i64] }, i32… 3708 …// Src: (anyext:{ :[i64] } (setcc:{ :[i1] } (and:{ :[i64] } (shl:{ :[i64] } 1:{ :[i64] }, i32… 3726 …// Src: (anyext:{ :[i32] } (setcc:{ :[i1] } (and:{ :[i32] } (shl:{ :[i32] } 1:{ :[i32] }, i32… [all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
D	MipsGenDAGISel.inc	1412 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (shl:{ :[i64] } 1:… 1426 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (shl:{ :[i64] } 1:… 1454 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (shl:{ :[i64] } 42… 1468 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (shl:{ :[i64] } 42… 1501 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } (shl:{ :[i64] } 1:{ :[i64] }, (imm:{ :[i64]… 1515 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } (shl:{ :[i64] } 1:{ :[i64] }, (imm:{ :[i64]… 1544 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } (shl:{ :[i64] } 4294967296:{ :[i64] }, (imm:… 1558 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } (shl:{ :[i64] } 4294967296:{ :[i64] }, (imm:… 1586 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } i64:{ :[i64] }:$lhs, (imm:{ :[i64] })<<P:Pre… 1607 …// Src: (brcond (setcc:{ :[i32] } (and:{ :[i64] } i64:{ :[i64] }:$lhs, (imm:{ :[i64] })<<P:Pre… [all …]
/external/llvm/lib/Target/NVPTX/
D	NVPTXVector.td	`948 // setcc convenience fragments. 950 (setcc node:$lhs, node:$rhs, SETOEQ)>; 952 (setcc node:$lhs, node:$rhs, SETOGT)>; 954 (setcc node:$lhs, node:$rhs, SETOGE)>; 956 (setcc node:$lhs, node:$rhs, SETOLT)>; 958 (setcc node:$lhs, node:$rhs, SETOLE)>; 960 (setcc node:$lhs, node:$rhs, SETONE)>; 962 (setcc node:$lhs, node:$rhs, SETO)>; 964 (setcc node:$lhs, node:$rhs, SETUO)>; 966 (setcc node:$lhs, node:$rhs, SETUEQ)>; [all …]`

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