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/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dadd.ll113 ; GP32: sltu $[[T1:[0-9]+]], $3, $5
120 ; MM32: sltu $[[T1:[0-9]+]], $3, $5
137 ; PRE4: sltu $[[R7:[0-9]+]], $[[R6]], $7
142 ; PRE4: sltu $[[R7]], $[[R8]], $6
148 ; PRE4: sltu $[[R17:[0-9]+]], $[[R15]], $[[R13]]
149 ; PRE4: sltu $[[R18:[0-9]+]], $[[R13]], $[[R1]]
157 ; GP32-CMOV: sltu $[[T4:[0-9]+]], $[[T3]], $7
159 ; GP32-CMOV: sltu $[[T6:[0-9]+]], $[[T5]], $6
166 ; GP32-CMOV: sltu $[[T13:[0-9]+]], $[[T11]], $[[T10]]
168 ; GP32-CMOV: sltu $[[T15:[0-9]+]], $[[T10]], $5
[all …]
Dsub.ll101 ; GP32: sltu $[[T0:[0-9]+]], $5, $7
106 ; MM32: sltu $[[T0:[0-9]+]], $5, $7
123 ; PRE4: sltu $[[T2:[0-9]+]], $7, $[[T1]]
128 ; PRE4: sltu $[[T5]], $6, $[[T0]]
133 ; PRE4: sltu $[[T9:[0-9]+]], $[[T7]], $[[T5]]
134 ; PRE4: sltu $[[T10:[0-9]+]], $5, $[[T6]]
144 ; MMR3: sltu $[[T2:[0-9]+]], $6, $[[T1]]
147 ; MMR3: sltu $[[T5:[0-9]+]], $7, $[[T4]]
152 ; MMR3: sltu $[[T10:[0-9]+]], $[[T8]], $[[T2]]
153 ; MMR3: sltu $[[T11:[0-9]+]], $5, $[[T7]]
[all …]
/external/llvm-project/llvm/test/MC/Mips/
Dmacro-sne.s8 # ALL: sltu $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2b]
10 # ALL: sltu $4, $zero, $6 # encoding: [0x00,0x06,0x20,0x2b]
12 # ALL: sltu $4, $zero, $5 # encoding: [0x00,0x05,0x20,0x2b]
14 # ALL: sltu $4, $zero, $5 # encoding: [0x00,0x05,0x20,0x2b]
20 # ALL: sltu $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2b]
23 # ALL: sltu $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2b]
27 # ALL: sltu $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2b]
Dmips64-instalias-imm-expanding.s640 sltu $4, -0x80000000
642 # CHECK-NEXT: sltu $4, $4, $1 # encoding: [0x2b,0x20,0x81,0x00]
643 sltu $4, -0x8001
646 # CHECK-NEXT: sltu $4, $4, $1 # encoding: [0x2b,0x20,0x81,0x00]
647 sltu $4, -0x8000
649 sltu $4, 0
651 sltu $4, 0xFFFF
653 # CHECK-NEXT: sltu $4, $4, $1 # encoding: [0x2b,0x20,0x81,0x00]
654 sltu $4, 0x10000
656 # CHECK-NEXT: sltu $4, $4, $1 # encoding: [0x2b,0x20,0x81,0x00]
[all …]
Dmacro-sgt.s12 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
14 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
17 # CHECK: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
24 # CHECK: sltu $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2b]
Dmacro-sle.s15 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
18 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
22 # CHECK: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
30 # CHECK: sltu $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2b]
Dmacro-sge.s21 # CHECK: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
24 # CHECK: sltu $4, $5, $6 # encoding: [0x00,0xa6,0x20,0x2b]
34 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
42 # CHECK: sltu $4, $4, $1 # encoding: [0x00,0x81,0x20,0x2b]
Dmacro-bcc-imm.s61 # ALL: sltu $1, $6, $1
65 # ALL: sltu $1, $1, $6
69 # ALL: sltu $1, $6, $1
73 # ALL: sltu $1, $1, $6
93 # ALL: sltu $1, $6, $1
97 # ALL: sltu $1, $1, $6
101 # ALL: sltu $1, $6, $1
105 # ALL: sltu $1, $1, $6
Dbranch-pseudos.s31 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
36 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
74 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
79 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
123 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
128 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
171 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
176 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
282 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
287 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dadd.ll108 ; GP32: sltu $[[T0:[0-9]+]], $3, $7
115 ; MM32: sltu $[[T0:[0-9]+]], $3, $7
131 ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
137 ; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
140 ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
147 ; GP64: sltu $[[T0:[0-9]+]], $3, $7
153 ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
157 ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
162 ; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]]
169 ; MM64: sltu $[[T0:[0-9]+]], $3, $7
[all …]
Dsub.ll103 ; GP32: sltu $[[T0:[0-9]+]], $5, $7
118 ; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]]
125 ; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]]
128 ; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]]
134 ; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
141 ; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]]
144 ; GP32-MM: sltu $[[T2]], $7, $[[T4]]
150 ; GP64: sltu $[[T0:[0-9]+]], $5, $7
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dicmp.ll20 ; MIPS32-NEXT: sltu $2, $zero, $1
77 ; MIPS32-NEXT: sltu $2, $5, $4
88 ; MIPS32-NEXT: sltu $1, $4, $5
100 ; MIPS32-NEXT: sltu $2, $4, $5
111 ; MIPS32-NEXT: sltu $1, $5, $4
137 ; MIPS32-NEXT: sltu $2, $1, $2
180 ; MIPS32-NEXT: sltu $2, $zero, $1
194 ; MIPS32-NEXT: sltu $1, $6, $4
211 ; MIPS32-NEXT: sltu $1, $4, $6
228 ; MIPS32-NEXT: sltu $1, $4, $6
[all …]
Dmul.ll125 ; MIPS32-NEXT: sltu $4, $3, $4
128 ; MIPS32-NEXT: sltu $5, $3, $5
139 ; MIPS32-NEXT: sltu $5, $4, $5
142 ; MIPS32-NEXT: sltu $24, $4, $24
146 ; MIPS32-NEXT: sltu $15, $4, $15
150 ; MIPS32-NEXT: sltu $11, $4, $11
154 ; MIPS32-NEXT: sltu $10, $4, $10
188 ; MIPS32-NEXT: sltu $2, $zero, $2
/external/llvm/test/MC/Mips/
Dmacro-bcc-imm.s23 # ALL: sltu $1, $6, $1
27 # ALL: sltu $1, $1, $6
31 # ALL: sltu $1, $6, $1
35 # ALL: sltu $1, $1, $6
55 # ALL: sltu $1, $6, $1
59 # ALL: sltu $1, $1, $6
63 # ALL: sltu $1, $6, $1
67 # ALL: sltu $1, $1, $6
Dinstalias-imm-expanding.s209 sltu $4, $5, -0x80000000
211 # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
212 sltu $4, $5, -0x8001
215 # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
216 sltu $4, $5, -0x8000
218 sltu $4, $5, 0
220 sltu $4, $5, 0xFFFF
222 sltu $4, $5, 0x10000
224 # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
225 sltu $4, $5, 0xFFFFFFFF
Dbranch-pseudos.s31 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
36 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
74 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
79 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
123 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
128 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
171 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
176 # CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
282 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
287 # CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dconst-mult.ll70 ; MIPS32-NEXT: sltu $1, $2, $1
97 ; MIPS32-NEXT: sltu $1, $2, $1
103 ; MIPS32-NEXT: sltu $9, $3, $8
111 ; MIPS32-NEXT: sltu $5, $8, $5
118 ; MIPS32-NEXT: sltu $6, $1, $8
132 ; MIPS64-NEXT: sltu $3, $2, $3
149 ; MIPS32-NEXT: sltu $1, $2, $1
155 ; MIPS32-NEXT: sltu $9, $8, $3
157 ; MIPS32-NEXT: sltu $10, $zero, $8
158 ; MIPS32-NEXT: sltu $11, $zero, $2
[all …]
Dsetcc-se.ll19 ; CHECK: sltu ${{[0-9]+}}, $zero, $4
20 ; MMR6: sltu ${{[0-9]+}}, $zero, $4
124 ; CHECK: sltu ${{[0-9]+}}
125 ; MMR6: sltu ${{[0-9]+}}
161 ; CHECK: sltu ${{[0-9]+}}
162 ; MMR6: sltu ${{[0-9]+}}
Dllcarry.ll18 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
30 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
43 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
Dmadd-msub.ll26 ; 32R6-NEXT: sltu $1, $3, $1
70 ; 16-NEXT: sltu $3, $2
98 ; 32R6-NEXT: sltu $1, $3, $1
132 ; 16-NEXT: sltu $3, $2
159 ; 32R6-NEXT: sltu $1, $3, $1
198 ; 16-NEXT: sltu $3, $2
274 ; 32R6-NEXT: sltu $2, $6, $1
317 ; 16-NEXT: sltu $6, $2
347 ; 32R6-NEXT: sltu $2, $6, $3
381 ; 16-NEXT: sltu $6, $2
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dsel1.ll10 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
27 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
44 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
59 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
75 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
91 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
Dicmpa.ll47 ; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
48 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
67 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
68 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
87 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
88 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
106 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
108 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
126 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
128 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
/external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/
Dsel1.ll27 ; CHECK-NEXT: sltu $1, $zero, $1
45 ; CHECK-NEXT: sltu $1, $zero, $1
61 ; CHECK-NEXT: sltu $1, $zero, $1
78 ; CHECK-NEXT: sltu $1, $zero, $1
93 ; CHECK-NEXT: sltu $1, $zero, $1
110 ; CHECK-NEXT: sltu $1, $zero, $1
126 ; CHECK-NEXT: sltu $1, $zero, $1
Dicmpa.ll47 ; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
48 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
67 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
68 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
87 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
88 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
106 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
108 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
126 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
128 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
/external/llvm/test/CodeGen/Mips/
Dllcarry.ll17 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
30 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
43 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}

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