/external/llvm-project/llvm/test/Transforms/ConstantHoisting/AArch64/ |
D | const-hoist-intrinsics.ll | 12 ; CHECK-NEXT: [[BAR_0:%.*]] = call i32 @llvm.aarch64.stxr.p0i64(i64 [[CONST_MAT]], i64* [[PTR_0]… 14 ; CHECK-NEXT: [[BAR_1:%.*]] = call i32 @llvm.aarch64.stxr.p0i64(i64 [[CONST]], i64* [[PTR_1]]) 17 ; CHECK-NEXT: [[BAR_2:%.*]] = call i32 @llvm.aarch64.stxr.p0i64(i64 [[CONST_MAT1]], i64* [[PTR_2… 20 ; CHECK-NEXT: [[BAR_3:%.*]] = call i32 @llvm.aarch64.stxr.p0i64(i64 [[CONST_MAT2]], i64* [[PTR_3… 25 %bar.0 = call i32 @llvm.aarch64.stxr.p0i64(i64 -9223372036317904896, i64* %ptr.0) 27 %bar.1 = call i32 @llvm.aarch64.stxr.p0i64(i64 -9223372036317904832, i64* %ptr.1) 29 %bar.2 = call i32 @llvm.aarch64.stxr.p0i64(i64 -9223372036317904768, i64* %ptr.2) 31 %bar.3 = call i32 @llvm.aarch64.stxr.p0i64(i64 -9223372036317904704, i64* %ptr.3) 35 declare i32 @llvm.aarch64.stxr.p0i64(i64 , i64*)
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/external/llvm-project/llvm/test/CodeGen/AArch64/ |
D | arm64_32-atomics.ll | 154 declare i32 @llvm.aarch64.stxr.p0i8(i64, i8*) 155 declare i32 @llvm.aarch64.stxr.p0i16(i64, i16*) 156 declare i32 @llvm.aarch64.stxr.p0i32(i64, i32*) 157 declare i32 @llvm.aarch64.stxr.p0i64(i64, i64*) 165 %success = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr) 175 %success = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr) 181 ; CHECK: stxr [[TMP:w[0-9]+]], w1, [x0] 185 %success = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr) 191 ; CHECK: stxr [[TMP:w[0-9]+]], x1, [x0] 194 %success = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr)
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D | arm64-ldxr-stxr.ll | 125 %res = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr) 140 %res = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr) 149 ; CHECK: stxr w0, w1, [x2] 153 ; GISEL: stxr w0, w1, [x2] 155 %res = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr) 162 ; CHECK: stxr w0, x1, [x2] 164 ; GISEL: stxr w0, x1, [x2] 165 %res = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr) 169 declare i32 @llvm.aarch64.stxr.p0i8(i64, i8*) nounwind 170 declare i32 @llvm.aarch64.stxr.p0i16(i64, i16*) nounwind [all …]
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D | arm64-atomic.ll | 12 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]] 31 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0] 72 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]] 133 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
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D | atomic-ops.ll | 120 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 207 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 352 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 436 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 576 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 683 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]] 782 ; OUTLINE_ATOMICS-NEXT: stxr w11, w10, [x9] 801 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 976 ; OUTLINE_ATOMICS-NEXT: stxr w11, x10, [x9] 995 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] [all …]
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D | atomic-ops-lse.ll | 3787 ; OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9] 3814 ; OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9] 3841 ; OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8] 3866 ; OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8] 3947 ; OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9] 3974 ; OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9] 4001 ; OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8] 4026 ; OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8] 4587 ; OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9] 4614 ; OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9] [all …]
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-ldxr-stxr.ll | 99 %res = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr) 109 %res = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr) 117 ; CHECK: stxr w0, w1, [x2] 119 %res = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr) 125 ; CHECK: stxr w0, x1, [x2] 126 %res = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr) 130 declare i32 @llvm.aarch64.stxr.p0i8(i64, i8*) nounwind 131 declare i32 @llvm.aarch64.stxr.p0i16(i64, i16*) nounwind 132 declare i32 @llvm.aarch64.stxr.p0i32(i64, i32*) nounwind 133 declare i32 @llvm.aarch64.stxr.p0i64(i64, i64*) nounwind
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D | arm64-atomic.ll | 10 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]] 28 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0] 65 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]] 124 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
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D | atomic-ops.ll | 87 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 147 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 247 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 307 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 407 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 483 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]] 557 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 679 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] 968 ; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]]
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/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
D | select-stx.mir | 36 …%5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volati… 67 …%5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volati… 93 …%4:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %3(s64), %2(p0) :: (volati… 118 …%3:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %1(s64), %2(p0) :: (volati…
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/external/llvm-project/llvm/test/Transforms/AtomicExpand/AArch64/ |
D | expand-atomicrmw-xchg-fp.ll | 14 ; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0f16(i64 [[TMP5]], half* [[PTR]]) 37 ; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0f32(i64 [[TMP5]], float* [[PTR]]) 58 ; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.aarch64.stxr.p0f64(i64 [[TMP3]], double* [[PTR]])
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/external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-canonical-form.txt | 5 # CHECK: stxr w0, x0, [x0]
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D | arm64-memory.txt | 456 # CHECK: stxr w1, x4, [x3] 457 # CHECK: stxr w1, w4, [x3]
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-canonical-form.txt | 5 # CHECK: stxr w0, x0, [x0]
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D | arm64-memory.txt | 456 # CHECK: stxr w1, x4, [x3] 457 # CHECK: stxr w1, w4, [x3]
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/external/arm-trusted-firmware/lib/locks/exclusive/aarch64/ |
D | spinlock.S | 56 stxr w1, w2, [x0]
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/external/llvm/test/MC/AArch64/ |
D | arm64-memory.s | 468 stxr w1, x4, [x3] 469 stxr w1, w4, [x3] 475 ; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8] 476 ; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
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/external/llvm-project/llvm/test/MC/AArch64/ |
D | arm64-memory.s | 468 stxr w1, x4, [x3] 469 stxr w1, w4, [x3] 475 ; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8] 476 ; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
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D | arm64-diags.s | 255 stxr w9, w9, [x12] 257 stxr w4, x4, [x9] 272 ; CHECK-ERRORS: stxr w9, w9, [x12] 278 ; CHECK-ERRORS: stxr w4, x4, [x9]
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D | basic-a64-instructions.s | 2242 stxr wzr, w4, [sp] 2243 stxr w5, x6, [x7]
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/external/llvm-project/lld/test/ELF/ |
D | aarch64-cortex-a53-843419-recognize.s | 521 stxr w4, x3, [x0]
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/external/vixl/ |
D | README.md | 124 `stxrb`, `stxrh`, `stxr`, `ldxrb`, `ldxrh`, `ldxr`, `stxp`, `ldxp`, `stlxrb`,
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/external/vixl/test/aarch64/ |
D | test-disasm-aarch64.cc | 1563 COMPARE(stxr(w20, w21, MemOperand(x22)), "stxr w20, w21, [x22]"); in TEST() 1564 COMPARE(stxr(x23, w24, MemOperand(sp)), "stxr w23, w24, [sp]"); in TEST() 1565 COMPARE(stxr(w25, x26, MemOperand(x27)), "stxr w25, x26, [x27]"); in TEST() 1566 COMPARE(stxr(x28, x29, MemOperand(sp)), "stxr w28, x29, [sp]"); in TEST()
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/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
D | A55-basic-instructions.s | 855 stxr w5, w6, [x17] label 856 stxr w1, x10, [x21] label 2112 # CHECK-NEXT: 2 7 1.00 * * U stxr w5, w6, [x17] 2113 # CHECK-NEXT: 2 7 1.00 * * U stxr w1, x10, [x21] 3295 … - - - - - - - - 1.00 - 1.00 stxr w5, w6, [x17] 3296 … - - - - - - - - 1.00 - 1.00 stxr w1, x10, [x21]
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/external/capstone/suite/MC/AArch64/ |
D | basic-a64-instructions.s.cs | 878 0xe4,0x7f,0x1f,0x88 = stxr wzr, w4, [sp] 879 0xe6,0x7c,0x05,0xc8 = stxr w5, x6, [x7]
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