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/external/llvm-project/llvm/test/CodeGen/Mips/
Dload-store-left-right.ll60 ; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
63 ; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
69 ; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
72 ; MIPS64R2-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
75 ; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
78 ; MIPS64R2-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
209 ; MIPS32-EL-DAG: swl $[[A1:4]], 3($[[R1:[0-9]+]])
211 ; MIPS32-EL-DAG: swl $[[A2:5]], 7($[[R1:[0-9]+]])
214 ; MIPS32-EB-DAG: swl $[[A1:4]], 0($[[R1:[0-9]+]])
216 ; MIPS32-EB-DAG: swl $[[A1:5]], 4($[[R1:[0-9]+]])
[all …]
Dswzero.ll7 ; CHECK: swl $zero
Dunaligned-memops-mapping.mir117 # CHECK: 8: 60 25 80 00 swl $1, 0($5)
/external/llvm-project/llvm/test/MC/Mips/
Dmicromips-loadstore-unaligned.s14 # CHECK-EL: swl $4, 16($5) # encoding: [0x85,0x60,0x10,0x80]
21 # CHECK-EB: swl $4, 16($5) # encoding: [0x60,0x85,0x80,0x10]
25 swl $4, 16($5)
Dmips-expansions.s1264 # CHECK-BE: swl $8, 0($zero) # encoding: [0xa8,0x08,0x00,0x00]
1266 # CHECK-LE: swl $8, 3($zero) # encoding: [0x03,0x00,0x08,0xa8]
1270 # CHECK-BE: swl $8, 2($zero) # encoding: [0xa8,0x08,0x00,0x02]
1272 # CHECK-LE: swl $8, 5($zero) # encoding: [0x05,0x00,0x08,0xa8]
1279 # CHECK-BE: swl $8, 0($1) # encoding: [0xa8,0x28,0x00,0x00]
1283 # CHECK-LE: swl $8, 3($1) # encoding: [0x03,0x00,0x28,0xa8]
1287 # CHECK-BE: swl $8, -32768($zero) # encoding: [0xa8,0x08,0x80,0x00]
1289 # CHECK-LE: swl $8, -32765($zero) # encoding: [0x03,0x80,0x08,0xa8]
1296 # CHECK-BE: swl $8, 0($1) # encoding: [0xa8,0x28,0x00,0x00]
1300 # CHECK-LE: swl $8, 3($1) # encoding: [0x03,0x00,0x28,0xa8]
[all …]
Dmips-memory-instructions.s13 # CHECK: swl $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa8]
20 swl $4, 16($5)
Dnacl-mask.s118 swl $4, 0($6)
149 # CHECK-NEXT: swl $4, 0($6)
/external/llvm/test/MC/Mips/
Dmicromips-loadstore-unaligned.s14 # CHECK-EL: swl $4, 16($5) # encoding: [0x85,0x60,0x10,0x80]
21 # CHECK-EB: swl $4, 16($5) # encoding: [0x60,0x85,0x80,0x10]
25 swl $4, 16($5)
Dmips-memory-instructions.s13 # CHECK: swl $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa8]
20 swl $4, 16($5)
Dnacl-mask.s118 swl $4, 0($6)
149 # CHECK-NEXT: swl $4, 0($6)
/external/llvm/test/CodeGen/Mips/
Dload-store-left-right.ll54 ; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
57 ; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
63 ; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
66 ; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
177 ; MIPS32-EL-DAG: swl $[[A1:4]], 3($[[R1:[0-9]+]])
179 ; MIPS32-EL-DAG: swl $[[A2:5]], 7($[[R1:[0-9]+]])
182 ; MIPS32-EB-DAG: swl $[[A1:4]], 0($[[R1:[0-9]+]])
184 ; MIPS32-EB-DAG: swl $[[A1:5]], 4($[[R1:[0-9]+]])
208 ; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
211 ; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
[all …]
Dswzero.ll7 ; CHECK: swl $zero
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dstore_split_because_of_memsize_or_align.ll124 ; MIPS32-NEXT: swl $6, 3($4)
145 ; MIPS32-NEXT: swl $6, 3($4)
208 ; MIPS32-NEXT: swl $6, 3($4)
231 ; MIPS32-NEXT: swl $6, 3($4)
294 ; MIPS32-NEXT: swl $6, 3($4)
325 ; MIPS32-NEXT: swl $6, 3($4)
412 ; MIPS32-NEXT: swl $3, 3($2)
414 ; MIPS32-NEXT: swl $1, 7($2)
437 ; MIPS32-NEXT: swl $3, 3($2)
439 ; MIPS32-NEXT: swl $1, 7($2)
[all …]
Dstore_4_unaligned.ll20 ; MIPS32-NEXT: swl $1, 3($2)
42 ; MIPS32-NEXT: swl $1, 3($2)
103 ; MIPS32-NEXT: swl $4, 3($1)
124 ; MIPS32-NEXT: swl $4, 3($1)
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
Dldr_str.ll128 ; MIPS32R5-EB-NEXT: swl $2, 16($5)
130 ; MIPS32R5-EB-NEXT: swl $1, 20($5)
140 ; MIPS32R5-EL-NEXT: swl $2, 19($5)
142 ; MIPS32R5-EL-NEXT: swl $1, 23($5)
184 ; MIPS32R5-EB-NEXT: swl $1, 16($5)
193 ; MIPS32R5-EL-NEXT: swl $1, 19($5)
/external/capstone/suite/MC/Mips/
Dmicromips-loadstore-unaligned.s.cs4 0x85,0x60,0x10,0x80 = swl $a0, 16($a1)
Dmicromips-loadstore-unaligned-EB.s.cs4 0x60,0x85,0x80,0x10 = swl $a0, 16($a1)
Dmips-memory-instructions.s.cs8 0x10,0x00,0xa4,0xa8 = swl $a0, 16($a1)
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips1-wrong-error.s12 …swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
Dinvalid-mips3-wrong-error.s18 …swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
/external/llvm-project/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips1-wrong-error.s12 …swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
Dinvalid-mips3-wrong-error.s18 …swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
/external/llvm-project/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips1-wrong-error.s12 …swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips1-wrong-error.s12 …swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
/external/llvm/test/MC/Mips/mips1/
Dvalid.s118 swl $15,13694($s3)
169 swl $3, %lo(g_8)($2) # CHECK: encoding: [0xa8,0x43,A,A]

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