1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB 3; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL 4; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB 5; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL 6; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 7; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 8 9; Test intrinsics for 4-byte and 8-byte MSA load and stores. 10 11define void @llvm_mips_ldr_d_test(<2 x i64>* %val, i8* %ptr) nounwind { 12; MIPS32R5-EB-LABEL: llvm_mips_ldr_d_test: 13; MIPS32R5-EB: # %bb.0: # %entry 14; MIPS32R5-EB-NEXT: # implicit-def: $v0 15; MIPS32R5-EB-NEXT: lwr $2, 23($5) 16; MIPS32R5-EB-NEXT: lwl $2, 20($5) 17; MIPS32R5-EB-NEXT: # implicit-def: $at 18; MIPS32R5-EB-NEXT: lwr $1, 19($5) 19; MIPS32R5-EB-NEXT: lwl $1, 16($5) 20; MIPS32R5-EB-NEXT: fill.w $w0, $2 21; MIPS32R5-EB-NEXT: insert.w $w0[1], $1 22; MIPS32R5-EB-NEXT: st.d $w0, 0($4) 23; MIPS32R5-EB-NEXT: jr $ra 24; MIPS32R5-EB-NEXT: nop 25; 26; MIPS32R5-EL-LABEL: llvm_mips_ldr_d_test: 27; MIPS32R5-EL: # %bb.0: # %entry 28; MIPS32R5-EL-NEXT: # implicit-def: $v0 29; MIPS32R5-EL-NEXT: lwr $2, 16($5) 30; MIPS32R5-EL-NEXT: lwl $2, 19($5) 31; MIPS32R5-EL-NEXT: # implicit-def: $at 32; MIPS32R5-EL-NEXT: lwr $1, 20($5) 33; MIPS32R5-EL-NEXT: lwl $1, 23($5) 34; MIPS32R5-EL-NEXT: fill.w $w0, $2 35; MIPS32R5-EL-NEXT: insert.w $w0[1], $1 36; MIPS32R5-EL-NEXT: st.d $w0, 0($4) 37; MIPS32R5-EL-NEXT: jr $ra 38; MIPS32R5-EL-NEXT: nop 39; 40; MIPS32R6-EB-LABEL: llvm_mips_ldr_d_test: 41; MIPS32R6-EB: # %bb.0: # %entry 42; MIPS32R6-EB-NEXT: lw $2, 20($5) 43; MIPS32R6-EB-NEXT: lw $1, 16($5) 44; MIPS32R6-EB-NEXT: fill.w $w0, $2 45; MIPS32R6-EB-NEXT: insert.w $w0[1], $1 46; MIPS32R6-EB-NEXT: st.d $w0, 0($4) 47; MIPS32R6-EB-NEXT: jrc $ra 48; 49; MIPS32R6-EL-LABEL: llvm_mips_ldr_d_test: 50; MIPS32R6-EL: # %bb.0: # %entry 51; MIPS32R6-EL-NEXT: lw $2, 16($5) 52; MIPS32R6-EL-NEXT: lw $1, 20($5) 53; MIPS32R6-EL-NEXT: fill.w $w0, $2 54; MIPS32R6-EL-NEXT: insert.w $w0[1], $1 55; MIPS32R6-EL-NEXT: st.d $w0, 0($4) 56; MIPS32R6-EL-NEXT: jrc $ra 57; 58; MIPS64R6-LABEL: llvm_mips_ldr_d_test: 59; MIPS64R6: # %bb.0: # %entry 60; MIPS64R6-NEXT: ld $1, 16($5) 61; MIPS64R6-NEXT: fill.d $w0, $1 62; MIPS64R6-NEXT: st.d $w0, 0($4) 63; MIPS64R6-NEXT: jrc $ra 64entry: 65 %0 = tail call <2 x i64> @llvm.mips.ldr.d(i8* %ptr, i32 16) 66 store <2 x i64> %0, <2 x i64>* %val 67 ret void 68} 69 70declare <2 x i64> @llvm.mips.ldr.d(i8*, i32) nounwind 71 72define void @llvm_mips_ldr_w_test(<4 x i32>* %val, i8* %ptr) nounwind { 73; MIPS32R5-EB-LABEL: llvm_mips_ldr_w_test: 74; MIPS32R5-EB: # %bb.0: # %entry 75; MIPS32R5-EB-NEXT: # implicit-def: $at 76; MIPS32R5-EB-NEXT: lwr $1, 19($5) 77; MIPS32R5-EB-NEXT: lwl $1, 16($5) 78; MIPS32R5-EB-NEXT: fill.w $w0, $1 79; MIPS32R5-EB-NEXT: st.w $w0, 0($4) 80; MIPS32R5-EB-NEXT: jr $ra 81; MIPS32R5-EB-NEXT: nop 82; 83; MIPS32R5-EL-LABEL: llvm_mips_ldr_w_test: 84; MIPS32R5-EL: # %bb.0: # %entry 85; MIPS32R5-EL-NEXT: # implicit-def: $at 86; MIPS32R5-EL-NEXT: lwr $1, 16($5) 87; MIPS32R5-EL-NEXT: lwl $1, 19($5) 88; MIPS32R5-EL-NEXT: fill.w $w0, $1 89; MIPS32R5-EL-NEXT: st.w $w0, 0($4) 90; MIPS32R5-EL-NEXT: jr $ra 91; MIPS32R5-EL-NEXT: nop 92; 93; MIPS32R6-EB-LABEL: llvm_mips_ldr_w_test: 94; MIPS32R6-EB: # %bb.0: # %entry 95; MIPS32R6-EB-NEXT: lw $1, 16($5) 96; MIPS32R6-EB-NEXT: fill.w $w0, $1 97; MIPS32R6-EB-NEXT: st.w $w0, 0($4) 98; MIPS32R6-EB-NEXT: jrc $ra 99; 100; MIPS32R6-EL-LABEL: llvm_mips_ldr_w_test: 101; MIPS32R6-EL: # %bb.0: # %entry 102; MIPS32R6-EL-NEXT: lw $1, 16($5) 103; MIPS32R6-EL-NEXT: fill.w $w0, $1 104; MIPS32R6-EL-NEXT: st.w $w0, 0($4) 105; MIPS32R6-EL-NEXT: jrc $ra 106; 107; MIPS64R6-LABEL: llvm_mips_ldr_w_test: 108; MIPS64R6: # %bb.0: # %entry 109; MIPS64R6-NEXT: lw $1, 16($5) 110; MIPS64R6-NEXT: fill.w $w0, $1 111; MIPS64R6-NEXT: st.w $w0, 0($4) 112; MIPS64R6-NEXT: jrc $ra 113entry: 114 %0 = tail call <4 x i32> @llvm.mips.ldr.w(i8* %ptr, i32 16) 115 store <4 x i32> %0, <4 x i32>* %val 116 ret void 117} 118 119declare <4 x i32> @llvm.mips.ldr.w(i8*, i32) nounwind 120 121define void @llvm_mips_str_d_test(<2 x i64>* %val, i8* %ptr) nounwind { 122; MIPS32R5-EB-LABEL: llvm_mips_str_d_test: 123; MIPS32R5-EB: # %bb.0: # %entry 124; MIPS32R5-EB-NEXT: ld.d $w0, 0($4) 125; MIPS32R5-EB-NEXT: copy_s.w $2, $w0[0] 126; MIPS32R5-EB-NEXT: copy_s.w $1, $w0[1] 127; MIPS32R5-EB-NEXT: swr $2, 19($5) 128; MIPS32R5-EB-NEXT: swl $2, 16($5) 129; MIPS32R5-EB-NEXT: swr $1, 23($5) 130; MIPS32R5-EB-NEXT: swl $1, 20($5) 131; MIPS32R5-EB-NEXT: jr $ra 132; MIPS32R5-EB-NEXT: nop 133; 134; MIPS32R5-EL-LABEL: llvm_mips_str_d_test: 135; MIPS32R5-EL: # %bb.0: # %entry 136; MIPS32R5-EL-NEXT: ld.d $w0, 0($4) 137; MIPS32R5-EL-NEXT: copy_s.w $2, $w0[0] 138; MIPS32R5-EL-NEXT: copy_s.w $1, $w0[1] 139; MIPS32R5-EL-NEXT: swr $2, 16($5) 140; MIPS32R5-EL-NEXT: swl $2, 19($5) 141; MIPS32R5-EL-NEXT: swr $1, 20($5) 142; MIPS32R5-EL-NEXT: swl $1, 23($5) 143; MIPS32R5-EL-NEXT: jr $ra 144; MIPS32R5-EL-NEXT: nop 145; 146; MIPS32R6-EB-LABEL: llvm_mips_str_d_test: 147; MIPS32R6-EB: # %bb.0: # %entry 148; MIPS32R6-EB-NEXT: ld.d $w0, 0($4) 149; MIPS32R6-EB-NEXT: copy_s.w $2, $w0[0] 150; MIPS32R6-EB-NEXT: copy_s.w $1, $w0[1] 151; MIPS32R6-EB-NEXT: sw $2, 20($5) 152; MIPS32R6-EB-NEXT: sw $1, 16($5) 153; MIPS32R6-EB-NEXT: jrc $ra 154; 155; MIPS32R6-EL-LABEL: llvm_mips_str_d_test: 156; MIPS32R6-EL: # %bb.0: # %entry 157; MIPS32R6-EL-NEXT: ld.d $w0, 0($4) 158; MIPS32R6-EL-NEXT: copy_s.w $2, $w0[0] 159; MIPS32R6-EL-NEXT: copy_s.w $1, $w0[1] 160; MIPS32R6-EL-NEXT: sw $2, 16($5) 161; MIPS32R6-EL-NEXT: sw $1, 20($5) 162; MIPS32R6-EL-NEXT: jrc $ra 163; 164; MIPS64R6-LABEL: llvm_mips_str_d_test: 165; MIPS64R6: # %bb.0: # %entry 166; MIPS64R6-NEXT: ld.d $w0, 0($4) 167; MIPS64R6-NEXT: copy_s.d $1, $w0[0] 168; MIPS64R6-NEXT: sd $1, 16($5) 169; MIPS64R6-NEXT: jrc $ra 170entry: 171 %0 = load <2 x i64>, <2 x i64>* %val 172 tail call void @llvm.mips.str.d(<2 x i64> %0, i8* %ptr, i32 16) 173 ret void 174} 175 176declare void @llvm.mips.str.d(<2 x i64>, i8*, i32) nounwind 177 178define void @llvm_mips_str_w_test(<4 x i32>* %val, i8* %ptr) nounwind { 179; MIPS32R5-EB-LABEL: llvm_mips_str_w_test: 180; MIPS32R5-EB: # %bb.0: # %entry 181; MIPS32R5-EB-NEXT: ld.w $w0, 0($4) 182; MIPS32R5-EB-NEXT: copy_s.w $1, $w0[0] 183; MIPS32R5-EB-NEXT: swr $1, 19($5) 184; MIPS32R5-EB-NEXT: swl $1, 16($5) 185; MIPS32R5-EB-NEXT: jr $ra 186; MIPS32R5-EB-NEXT: nop 187; 188; MIPS32R5-EL-LABEL: llvm_mips_str_w_test: 189; MIPS32R5-EL: # %bb.0: # %entry 190; MIPS32R5-EL-NEXT: ld.w $w0, 0($4) 191; MIPS32R5-EL-NEXT: copy_s.w $1, $w0[0] 192; MIPS32R5-EL-NEXT: swr $1, 16($5) 193; MIPS32R5-EL-NEXT: swl $1, 19($5) 194; MIPS32R5-EL-NEXT: jr $ra 195; MIPS32R5-EL-NEXT: nop 196; 197; MIPS32R6-EB-LABEL: llvm_mips_str_w_test: 198; MIPS32R6-EB: # %bb.0: # %entry 199; MIPS32R6-EB-NEXT: ld.w $w0, 0($4) 200; MIPS32R6-EB-NEXT: copy_s.w $1, $w0[0] 201; MIPS32R6-EB-NEXT: sw $1, 16($5) 202; MIPS32R6-EB-NEXT: jrc $ra 203; 204; MIPS32R6-EL-LABEL: llvm_mips_str_w_test: 205; MIPS32R6-EL: # %bb.0: # %entry 206; MIPS32R6-EL-NEXT: ld.w $w0, 0($4) 207; MIPS32R6-EL-NEXT: copy_s.w $1, $w0[0] 208; MIPS32R6-EL-NEXT: sw $1, 16($5) 209; MIPS32R6-EL-NEXT: jrc $ra 210; 211; MIPS64R6-LABEL: llvm_mips_str_w_test: 212; MIPS64R6: # %bb.0: # %entry 213; MIPS64R6-NEXT: ld.w $w0, 0($4) 214; MIPS64R6-NEXT: copy_s.w $1, $w0[0] 215; MIPS64R6-NEXT: sw $1, 16($5) 216; MIPS64R6-NEXT: jrc $ra 217entry: 218 %0 = load <4 x i32>, <4 x i32>* %val 219 tail call void @llvm.mips.str.w(<4 x i32> %0, i8* %ptr, i32 16) 220 ret void 221} 222 223declare void @llvm.mips.str.w(<4 x i32>, i8*, i32) nounwind 224 225