Home
last modified time | relevance | path

Searched refs:tzdram_base (Results 1 – 11 of 11) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_secondary.c38 tzdram_addr = params_from_bl2->tzdram_base + in plat_secondary_setup()
48 memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base), in plat_secondary_setup()
53 addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; in plat_secondary_setup()
54 addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); in plat_secondary_setup()
Dplat_psci_handlers.c142 mc_ctx_base = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_suspend()
275 val = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_power_down_wfi()
303 val = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_power_down_wfi()
/external/arm-trusted-firmware/plat/nvidia/tegra/common/
Dtegra_bl31_setup.c130 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; in bl31_early_platform_setup2()
141 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && in bl31_early_platform_setup2()
308 mmap_add_region(params_from_bl2->tzdram_base, in bl31_plat_arch_setup()
309 params_from_bl2->tzdram_base, in bl31_plat_arch_setup()
Dtegra_pm.c184 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in tegra_pwr_domain_on_finish()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/
Dplat_setup.c174 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in plat_early_platform_setup()
221 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base); in plat_late_platform_setup()
225 assert(sc7entry_end < plat_params->tzdram_base); in plat_late_platform_setup()
228 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; in plat_late_platform_setup()
Dplat_psci_handlers.c491 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; in tegra_soc_pwr_domain_on_finish()
/external/arm-trusted-firmware/plat/nvidia/tegra/drivers/memctrl/
Dmemctrl_v2.c124 uint64_t tzdram_base = params_from_bl2->tzdram_base; in tegra_mc_save_context() local
125 uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size; in tegra_mc_save_context()
127 assert((mc_ctx_addr >= tzdram_base) && (mc_ctx_addr <= tzdram_end)); in tegra_mc_save_context()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_setup.c201 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in plat_early_platform_setup()
333 tzdram_start = plat_bl31_params->tzdram_base; in plat_relocate_bl32_image()
334 tzdram_end = plat_bl31_params->tzdram_base + in plat_relocate_bl32_image()
Dplat_psci_handlers.c142 mc_ctx_base = params_from_bl2->tzdram_base; in tegra_soc_pwr_domain_suspend()
292 val = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_power_down_wfi()
319 val = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_power_down_wfi()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/
Dplat_setup.c157 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in plat_early_platform_setup()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/
Dtegra_private.h39 uint64_t tzdram_base; member