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Searched refs:v1i32 (Results 1 – 25 of 68) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.image.sample-masked.ll9 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
22 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
35 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
48 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
61 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
73 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
85 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
92 declare <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32…
/external/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/
Dvecreduce.ll4 declare i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a)
6 declare i32 @llvm.vector.reduce.mul.v1i32(<1 x i32> %a)
8 declare i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)
10 declare i32 @llvm.vector.reduce.or.v1i32(<1 x i32> %a)
12 declare i32 @llvm.vector.reduce.xor.v1i32(<1 x i32> %a)
14 declare i32 @llvm.vector.reduce.smin.v1i32(<1 x i32> %a)
16 declare i32 @llvm.vector.reduce.smax.v1i32(<1 x i32> %a)
18 declare i32 @llvm.vector.reduce.umin.v1i32(<1 x i32> %a)
20 declare i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a)
52 %x = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> <i32 10>)
[all …]
/external/llvm-project/clang/test/CodeGen/RISCV/
Driscv32-ilp32-ilp32f-ilp32d-abi.c89 typedef int32_t v1i32 __attribute__((vector_size(4))); typedef
103 void f_vec_tiny_v1i32(v1i32 x) { in f_vec_tiny_v1i32()
108 v1i32 f_vec_tiny_v1i32_ret() { in f_vec_tiny_v1i32_ret()
109 return (v1i32){1}; in f_vec_tiny_v1i32_ret()
/external/clang/test/CodeGen/
Dsystemz-abi-vector.c17 typedef __attribute__((vector_size(4))) int v1i32; typedef
82 v1i32 pass_v1i32(v1i32 arg) { return arg; } in pass_v1i32()
/external/llvm-project/clang/test/CodeGen/SystemZ/
Dsystemz-abi-vector.c27 typedef __attribute__((vector_size(4))) int v1i32; typedef
92 v1i32 pass_v1i32(v1i32 arg) { return arg; } in pass_v1i32()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h87 v1i32 = 38, // 1 x i32 enumerator
235 SimpleTy == MVT::v1i32 || SimpleTy == MVT::v2f16 || in is32BitVector()
342 case v1i32: in getVectorElementType()
421 case v1i32: in getVectorNumElements()
466 case v1i32: return 32; in getSizeInBits()
624 if (NumElements == 1) return MVT::v1i32; in getVectorVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h92 v1i32 = 43, // 1 x i32 enumerator
336 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || in is32BitVector()
475 case v1i32: in getVectorElementType()
655 case v1i32: in getVectorNumElements()
725 case v1i32: return TypeSize::Fixed(32); in getSizeInBits()
958 if (NumElements == 1) return MVT::v1i32; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/ARM/
Dv1-constant-fold.ll3 ; PR15611. Check that we don't crash when constant folding v1i32 types.
/external/llvm/test/CodeGen/ARM/
Dv1-constant-fold.ll3 ; PR15611. Check that we don't crash when constant folding v1i32 types.
Dcttz_vector.ll16 declare <1 x i32> @llvm.cttz.v1i32(<1 x i32>, i1)
130 %tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 false)
312 %tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 true)
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td344 // D form - v1i8, v1i16, v1i32, v1i64
371 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
407 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
420 // D form - v1i32, v1i64
435 …yc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
442 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6…
473 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
482 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
497 // D form - v1i8, v1i16, v1i32, v1i64
511 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
11 ; FIXME: Currently XTN is generated for v1i32, but it can be optimized.
Dvecreduce-add-legalization.ll8 declare i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a)
63 %b = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a)
Dvecreduce-umax-legalization.ll8 declare i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a)
64 %b = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a)
Dvecreduce-and-legalization.ll8 declare i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)
63 %b = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)
/external/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
11 ; FIXME: Currently XTN is generated for v1i32, but it can be optimized.
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedA57.td348 // D form - v1i8, v1i16, v1i32, v1i64
375 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
411 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
424 // D form - v1i32, v1i64
439 …yc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
446 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6…
477 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
486 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
501 // D form - v1i8, v1i16, v1i32, v1i64
515 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
[all …]
DAArch64SchedFalkorDetails.td591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>;
598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>;
681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2…
685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"…
695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
703 … (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
707 … (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
[all …]
DAArch64SchedKryoDetails.td147 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
213 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
231 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
261 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
273 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;
693 (instregex "FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64)rz")>;
735 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
771 (instregex "FCVTZ(S|U)(v2f32|v1i32|v1i64|v2i32(_shift)?)$")>;
1818 (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>;
1824 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedA57.td347 // D form - v1i8, v1i16, v1i32, v1i64
374 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
410 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
423 // D form - v1i32, v1i64
438 …yc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
445 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6…
476 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
485 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
500 // D form - v1i8, v1i16, v1i32, v1i64
514 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
[all …]
DAArch64SchedFalkorDetails.td591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>;
598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>;
681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2…
685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"…
695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
703 … (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
707 … (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
[all …]
DAArch64SchedKryoDetails.td147 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
213 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
231 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
261 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
273 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;
693 (instregex "FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64)rz")>;
735 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
771 (instregex "FCVTZ(S|U)(v2f32|v1i32|v1i64|v2i32(_shift)?)$")>;
1818 (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>;
1824 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h93 v1i32 = 44, // 1 x i32 enumerator
365 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || in is32BitVector()
544 case v1i32: in getVectorElementType()
773 case v1i32: in getVectorNumElements()
852 case v1i32: return TypeSize::Fixed(32); in getSizeInBits()
1145 if (NumElements == 1) return MVT::v1i32; in getVectorVT()
/external/llvm/lib/IR/
DValueTypes.cpp170 case MVT::v1i32: return "v1i32"; in getEVTString()
248 case MVT::v1i32: return VectorType::get(Type::getInt32Ty(Context), 1); in getTypeForEVT()
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dmve-vecreduce-add.ll101 …estimated cost of 1 for instruction: %a0z = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a0za)
103 …estimated cost of 1 for instruction: %a0s = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a0sa)
121 …estimated cost of 1 for instruction: %a5z = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a5za)
123 …estimated cost of 1 for instruction: %a5s = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a5sa)
140 …estimated cost of 1 for instruction: %a10 = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> undef)
148 %a0z = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a0za)
151 %a0s = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a0sa)
178 %a5z = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a5za)
181 %a5s = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a5sa)
207 %a10 = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> undef)
[all …]

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