| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 76 v256i8 = 29, //256 x i8 enumerator
279 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
333 case v256i8: return i8; in getVectorElementType()
377 case v256i8: return 256; in getVectorNumElements()
508 case v256i8: in getSizeInBits()
611 if (NumElements == 256) return MVT::v256i8; in getVectorVT()
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| D | ValueTypes.td | 53 def v256i8 : ValueType<2048,29>; //256 x i8 vector value
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 102 CCIfType<[v64i32,v128i16,v256i8],
108 CCIfType<[v64i32,v128i16,v256i8],
128 CCIfType<[v64i32,v128i16,v256i8],
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| D | HexagonISelLoweringHVX.cpp | 19 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
47 addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
62 MVT ByteW = Use64b ? MVT::v128i8 : MVT::v256i8; in initializeHVXLowering()
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| D | HexagonRegisterInfo.td | 295 [v128i8, v256i8, v128i8]>;
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 132 CCIfType<[v64i32,v128i16,v256i8],
138 CCIfType<[v64i32,v128i16,v256i8],
158 CCIfType<[v64i32,v128i16,v256i8],
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| D | HexagonRegisterInfo.td | 331 [v128i8, v256i8, v128i8]>;
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| D | HexagonISelLoweringHVX.cpp | 24 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
51 addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
65 MVT ByteW = Use64b ? MVT::v128i8 : MVT::v256i8; in initializeHVXLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 80 v256i8 = 33, //256 x i8 enumerator
382 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
453 case v256i8: in getVectorElementType()
560 case v256i8: in getVectorNumElements()
811 case v256i8: in getSizeInBits()
944 if (NumElements == 256) return MVT::v256i8; in getVectorVT()
|
| /external/llvm-project/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 81 v256i8 = 34, //256 x i8 enumerator
417 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
521 case v256i8: in getVectorElementType()
653 case v256i8: in getVectorNumElements()
953 case v256i8: in getSizeInBits()
1131 if (NumElements == 256) return MVT::v256i8; in getVectorVT()
|
| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 161 case MVT::v256i8: return "v256i8"; in getEVTString()
239 case MVT::v256i8: return VectorType::get(Type::getInt8Ty(Context), 256); in getTypeForEVT()
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-fixed-length-int-reduce.ll | 99 %res = call i8 @llvm.vector.reduce.add.v256i8(<256 x i8> %op)
407 %res = call i8 @llvm.vector.reduce.smax.v256i8(<256 x i8> %op)
717 %res = call i8 @llvm.vector.reduce.smin.v256i8(<256 x i8> %op)
1027 %res = call i8 @llvm.vector.reduce.umax.v256i8(<256 x i8> %op)
1337 %res = call i8 @llvm.vector.reduce.umin.v256i8(<256 x i8> %op)
1578 declare i8 @llvm.vector.reduce.add.v256i8(<256 x i8>)
1606 declare i8 @llvm.vector.reduce.smax.v256i8(<256 x i8>)
1634 declare i8 @llvm.vector.reduce.smin.v256i8(<256 x i8>)
1662 declare i8 @llvm.vector.reduce.umax.v256i8(<256 x i8>)
1690 declare i8 @llvm.vector.reduce.umin.v256i8(<256 x i8>)
|
| D | sve-fixed-length-log-reduce.ll | 104 %res = call i8 @llvm.vector.reduce.and.v256i8(<256 x i8> %op)
427 %res = call i8 @llvm.vector.reduce.xor.v256i8(<256 x i8> %op)
750 %res = call i8 @llvm.vector.reduce.or.v256i8(<256 x i8> %op)
999 declare i8 @llvm.vector.reduce.and.v256i8(<256 x i8>)
1027 declare i8 @llvm.vector.reduce.or.v256i8(<256 x i8>)
1055 declare i8 @llvm.vector.reduce.xor.v256i8(<256 x i8>)
|
| D | sve-fixed-length-int-minmax.ll | 113 %res = call <256 x i8> @llvm.smax.v256i8(<256 x i8> %op1, <256 x i8> %op2)
485 %res = call <256 x i8> @llvm.smin.v256i8(<256 x i8> %op1, <256 x i8> %op2)
858 %res = call <256 x i8> @llvm.umax.v256i8(<256 x i8> %op1, <256 x i8> %op2)
1230 %res = call <256 x i8> @llvm.umin.v256i8(<256 x i8> %op1, <256 x i8> %op2)
1520 declare <256 x i8> @llvm.smin.v256i8(<256 x i8>, <256 x i8>)
1545 declare <256 x i8> @llvm.smax.v256i8(<256 x i8>, <256 x i8>)
1570 declare <256 x i8> @llvm.umin.v256i8(<256 x i8>, <256 x i8>)
1595 declare <256 x i8> @llvm.umax.v256i8(<256 x i8>, <256 x i8>)
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 210 LocVT == MVT::v256i8) { in CC_Hexagon_VarArg()
361 LocVT == MVT::v256i8)) { in CC_HexagonVector()
424 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 || in RetCC_Hexagon()
548 ty == MVT::v256i8 || in IsHvxVectorType()
1141 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { in LowerFormalArguments()
1769 addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
2004 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom); in HexagonTargetLowering()
2896 case MVT::v256i8: in getRegForInlineAsmConstraint()
3030 case MVT::v256i8: in allowsMisalignedMemoryAccesses()
3071 case MVT::v256i8: in findRepresentativeClass()
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| D | HexagonRegisterInfo.td | 238 [v256i8,v128i16,v64i32,v32i64], 2048,
|
| D | HexagonInstrInfoV60.td | 798 defm : STrivv_pats <v128i8, v256i8>;
873 defm : LDrivv_pats <v128i8, v256i8>;
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 89 case MVT::v256i8: return "MVT::v256i8"; in getEnumName()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 178 case MVT::v256i8: return VectorType::get(Type::getInt8Ty(Context), 256); in getTypeForEVT()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 55 def v256i8 : ValueType<2048,33>; //256 x i8 vector value
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 57 def v256i8 : ValueType<2048,34>; //256 x i8 vector value
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 236 case MVT::v256i8: in getTypeForEVT()
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 100 case MVT::v256i8: return "MVT::v256i8"; in getEnumName()
|
| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 186 def llvm_v256i8_ty : LLVMType<v256i8>; //256 x i8
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 246 def llvm_v256i8_ty : LLVMType<v256i8>; //256 x i8
|