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/external/llvm-project/clang/test/CodeGen/
Dbuiltins-mips.c11 typedef signed char v4i8 __attribute__ ((vector_size(4))); typedef
20 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; in foo()
28 v4i8_a = (v4i8) {1, 2, 3, 0xFF}; in foo()
29 v4i8_b = (v4i8) {2, 4, 6, 8}; in foo()
92 v4i8_a = (v4i8) {1, 2, 3, 4}; in foo()
125 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; in foo()
143 v4i8_a = (v4i8) {1, 2, 3, 4}; in foo()
146 v4i8_a = (v4i8) {128, 64, 32, 16}; in foo()
169 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; in foo()
212 v4i8_b = (v4i8) {1, 2, 3, 4}; in foo()
[all …]
/external/clang/test/CodeGen/
Dbuiltins-mips.c10 typedef signed char v4i8 __attribute__ ((vector_size(4))); typedef
19 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; in foo()
27 v4i8_a = (v4i8) {1, 2, 3, 0xFF}; in foo()
28 v4i8_b = (v4i8) {2, 4, 6, 8}; in foo()
91 v4i8_a = (v4i8) {1, 2, 3, 4}; in foo()
124 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; in foo()
142 v4i8_a = (v4i8) {1, 2, 3, 4}; in foo()
145 v4i8_a = (v4i8) {128, 64, 32, 16}; in foo()
168 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; in foo()
211 v4i8_b = (v4i8) {1, 2, 3, 4}; in foo()
[all …]
Dsystemz-abi-vector.c15 typedef __attribute__((vector_size(4))) char v4i8; typedef
50 v4i8 pass_v4i8(v4i8 arg) { return arg; } in pass_v4i8()
143 struct agg_v4i8 { v4i8 a; };
166 struct agg_novector1 { v4i8 a; v4i8 b; };
171 struct agg_novector2 { v4i8 a; float b; };
176 struct agg_novector3 { v4i8 a; int : 0; };
181 struct agg_novector4 { v4i8 a __attribute__((aligned (8))); };
253 v4i8 va_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, v4i8); } in va_v4i8()
/external/llvm-project/clang/test/CodeGen/SystemZ/
Dsystemz-abi-vector.c25 typedef __attribute__((vector_size(4))) char v4i8; typedef
60 v4i8 pass_v4i8(v4i8 arg) { return arg; } in pass_v4i8()
153 struct agg_v4i8 { v4i8 a; };
176 struct agg_novector1 { v4i8 a; v4i8 b; };
181 struct agg_novector2 { v4i8 a; float b; };
186 struct agg_novector3 { v4i8 a; int : 0; };
191 struct agg_novector4 { v4i8 a __attribute__((aligned (8))); };
263 v4i8 va_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, v4i8); } in va_v4i8()
/external/llvm-project/llvm/test/Analysis/CostModel/AArch64/
Dmem-op-cost-model.ll90 declare <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*>, i32 immarg, <4 x i1>, <4 x i8>)
93 …Found an estimated cost of 17 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8
94 …Found an estimated cost of 17 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8
95 …Found an estimated cost of 17 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8
96 …Found an estimated cost of 17 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8
98 …%lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true, i1 …
104 …Found an estimated cost of 29 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8
105 …Found an estimated cost of 29 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8
106 …Found an estimated cost of 29 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8
107 …Found an estimated cost of 29 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dneon-truncStore-extLoad.ll23 define void @truncStore.v4i8(<4 x i32> %a, <4 x i8>* %result) {
24 ; CHECK-LABEL: truncStore.v4i8:
44 define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
45 ; CHECK-LABEL: loadSExt.v4i8:
52 define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
53 ; CHECK-LABEL: loadZExt.v4i8:
/external/llvm-project/clang/test/Sema/
Dbuiltins-mips-features.c4 typedef signed char v4i8 __attribute__ ((vector_size(4))); typedef
10 v4i8 a; in dsp()
20 v4i8 a; in dspr2()
/external/llvm-project/lldb/test/API/commands/watchpoints/watchpoint_on_vectors/
Dmain.c1 typedef signed char v4i8 __attribute__ ((vector_size(4))); typedef
2 v4i8 global_vector = {1, 2, 3, 4};
/external/llvm/test/CodeGen/AArch64/
Dneon-truncStore-extLoad.ll34 define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
35 ; CHECK-LABEL: loadSExt.v4i8:
42 define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
43 ; CHECK-LABEL: loadZExt.v4i8:
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td17 def V4I8: PatLeaf<(v4i8 IntRegs:$R)>;
39 defm : bitconvert_32<v4i8, i32>;
89 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
253 // Adds two v4i8: Hexagon does not have an insn for this one, so we
255 def: Pat<(v4i8 (add (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
258 // Subtract two v4i8: Hexagon does not have an insn for this one, so we
260 def: Pat<(v4i8 (sub (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
266 def: Pat<(v4i8 (select I1:$Pu, V4I8:$Rs, V4I8:$Rt)),
328 def: Pat<(v4i8 (trunc V4I16:$Rs)),
391 // Multiplies two v4i8 vectors.
[all …]
/external/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/
Dfunnel-shift.ll8 declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
9 declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
66 …%f = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> <i8 0, i8 -1, i8 16, i8 17>, <4 x i8> <i8 -1, i8 0, i8…
80 …%f = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> <i8 0, i8 -1, i8 16, i8 17>, <4 x i8> <i8 -1, i8 0, i8…
203 …%f = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> <i8 undef, i8 1, i8 undef, i8 undef>, <4 x i8> <i8 und…
212 …%f = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> <i8 1, i8 undef, i8 -1, i8 7>, <4 x i8> <i8 undef, i8 …
221 …%f = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> <i8 undef, i8 1, i8 undef, i8 undef>, <4 x i8> <i8 und…
230 …%f = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> <i8 1, i8 undef, i8 -1, i8 7>, <4 x i8> <i8 undef, i8 …
/external/llvm-project/clang/test/CodeGen/RISCV/
Driscv32-ilp32-ilp32f-ilp32d-abi.c88 typedef uint8_t v4i8 __attribute__((vector_size(4))); typedef
92 void f_vec_tiny_v4i8(v4i8 x) { in f_vec_tiny_v4i8()
98 v4i8 f_vec_tiny_v4i8_ret() { in f_vec_tiny_v4i8_ret()
99 return (v4i8){1, 2, 3, 4}; in f_vec_tiny_v4i8_ret()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp589 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, in getCastInstrCost()
621 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
622 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
634 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, in getCastInstrCost()
652 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, in getCastInstrCost()
653 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, in getCastInstrCost()
668 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, in getCastInstrCost()
676 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
677 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, in getCastInstrCost()
689 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, in getCastInstrCost()
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dwith_overflow.ll601 declare { <4 x i8>, <4 x i1> } @llvm.sadd.with.overflow.v4i8(<4 x i8>, <4 x i8>)
602 declare { <4 x i8>, <4 x i1> } @llvm.uadd.with.overflow.v4i8(<4 x i8>, <4 x i8>)
603 declare { <4 x i8>, <4 x i1> } @llvm.ssub.with.overflow.v4i8(<4 x i8>, <4 x i8>)
604 declare { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8>, <4 x i8>)
605 declare { <4 x i8>, <4 x i1> } @llvm.smul.with.overflow.v4i8(<4 x i8>, <4 x i8>)
606 declare { <4 x i8>, <4 x i1> } @llvm.umul.with.overflow.v4i8(<4 x i8>, <4 x i8>)
614 …%x = call { <4 x i8>, <4 x i1> } @llvm.sadd.with.overflow.v4i8(<4 x i8> <i8 127, i8 127, i8 127, i…
622 …%x = call { <4 x i8>, <4 x i1> } @llvm.uadd.with.overflow.v4i8(<4 x i8> <i8 255, i8 255, i8 255, i…
630 …%x = call { <4 x i8>, <4 x i1> } @llvm.ssub.with.overflow.v4i8(<4 x i8> <i8 -128, i8 -128, i8 -128…
638 …%x = call { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8> <i8 0, i8 0, i8 0, i8 0>, …
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td15 CCIfType<[i32,v2i16,v4i8],
39 CCIfType<[i32,v2i16,v4i8],
69 CCIfType<[i32,v2i16,v4i8],
97 CCIfType<[i32,v2i16,v4i8],
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1341 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1343 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1345 def : BitconvertPat<f32, v4i8, FGR32, DSPR>;
1347 def : BitconvertPat<v4i8, f32, DSPR, FGR32>;
1351 def : DSPPat<(v4i8 (load addr:$a)),
1352 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1355 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1369 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1370 def : DSPBinPat<ADDU_QB, v4i8, add>;
1371 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1341 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1343 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1345 def : BitconvertPat<f32, v4i8, FGR32, DSPR>;
1347 def : BitconvertPat<v4i8, f32, DSPR, FGR32>;
1351 def : DSPPat<(v4i8 (load addr:$a)),
1352 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1355 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1369 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1370 def : DSPBinPat<ADDU_QB, v4i8, add>;
1371 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h70 v4i8 = 23, // 4 x i8 enumerator
234 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 || in is32BitVector()
327 case v4i8: in getVectorElementType()
404 case v4i8: in getVectorNumElements()
462 case v4i8: in getSizeInBits()
605 if (NumElements == 4) return MVT::v4i8; in getVectorVT()
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1318 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1320 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1324 def : DSPPat<(v4i8 (load addr:$a)),
1325 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1328 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1342 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1343 def : DSPBinPat<ADDU_QB, v4i8, add>;
1344 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1345 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1362 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td15 CCIfType<[i32,v2i16,v4i8],
39 CCIfType<[i32,v2i16,v4i8],
67 CCIfType<[i32,v2i16,v4i8],
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc557 /* 917*/ OPC_CheckChild1Type, MVT::v4i8,
569 …// Src: (st DSPR:{ *:[v4i8] }:$val, addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predica…
570 …// Dst: (SW (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$val, GPR32:{ *:[i32] }), addr:{ *:[iP…
1338 /* 2388*/ /*SwitchType*/ 25, MVT::v4i8,// ->2415
1346 MVT::v4i8, 2/*#Ops*/, 4, 5,
1347 …// Src: (ld:{ *:[v4i8] } addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - …
1348 … // Dst: (COPY_TO_REGCLASS:{ *:[v4i8] } (LW:{ *:[i32] } addr:{ *:[iPTR] }:$a), DSPR:{ *:[i32] })
7140 …trinsic_w_chain:{ *:[i32] } 3810:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$r…
7141 … // Dst: (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
7147 …trinsic_w_chain:{ *:[i32] } 3810:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$r…
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1034 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw in getShuffleCost()
1039 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus in getShuffleCost()
1045 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw in getShuffleCost()
1051 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw in getShuffleCost()
1422 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, in getCastInstrCost()
1435 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, in getCastInstrCost()
1449 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm in getCastInstrCost()
1483 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd in getCastInstrCost()
1512 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, in getCastInstrCost()
1513 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, in getCastInstrCost()
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dpr35443.ll19 …%wide.masked.load66 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* bitcast (i8* getelemen…
30 declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32, <4 x i1>, <4 x i8>)
/external/llvm-project/llvm/test/CodeGen/ARM/
D2012-08-23-legalize-vmull.ll13 ; v4i8
54 ; v4i8
104 ; v4i8 x v4i16
/external/llvm/test/CodeGen/ARM/
D2012-08-23-legalize-vmull.ll13 ; v4i8
54 ; v4i8
104 ; v4i8 x v4i16

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