| /external/mesa3d/src/compiler/nir/ |
| D | nir_lower_wrmasks.c | 108 unsigned wrmask = nir_intrinsic_write_mask(intr); in split_wrmask() local
109 while (wrmask) { in split_wrmask()
110 unsigned first_component = ffs(wrmask) - 1; in split_wrmask()
111 unsigned length = ffs(~(wrmask >> first_component)) - 1; in split_wrmask()
175 wrmask &= ~cur_mask; in split_wrmask()
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| D | nir_lower_clip_disable.c | 82 int wrmask = nir_intrinsic_write_mask(instr); in lower_clip_plane_store() local
88 if (wrmask & (1 << i)) { in lower_clip_plane_store()
96 nir_store_deref(b, deref, nir_vec(b, components, instr->num_components), wrmask); in lower_clip_plane_store()
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| D | nir_opt_copy_prop_vars.c | 1010 unsigned wrmask = nir_intrinsic_write_mask(intrin); in copy_prop_vars_block() local
1011 kill_aliases(copies, dst, wrmask); in copy_prop_vars_block()
1027 unsigned wrmask = nir_intrinsic_write_mask(intrin); in copy_prop_vars_block() local
1029 get_entry_and_kill_aliases(copies, vec_dst, wrmask); in copy_prop_vars_block()
1030 value_set_from_value(&entry->src, &value, vec_index, wrmask); in copy_prop_vars_block()
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| D | nir_lower_vars_to_ssa.c | 637 unsigned wrmask = nir_intrinsic_write_mask(intrin); in rename_variables() local
638 if (wrmask == (1 << intrin->num_components) - 1) { in rename_variables()
658 if (wrmask & (1 << i)) { in rename_variables()
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| D | nir_print.c | 871 unsigned wrmask = nir_intrinsic_write_mask(instr); in print_intrinsic_instr() local
874 if ((wrmask >> i) & 1) in print_intrinsic_instr()
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection.h | 205 unsigned wrmask = nir_intrinsic_write_mask(intrin); in can_subdword_ssbo_store_use_smem() local
206 if (util_last_bit(wrmask) != util_bitcount(wrmask) || in can_subdword_ssbo_store_use_smem()
207 util_bitcount(wrmask) * intrin->src[0].ssa->bit_size % 32 || in can_subdword_ssbo_store_use_smem()
208 util_bitcount(wrmask) != intrin->src[0].ssa->num_components) in can_subdword_ssbo_store_use_smem()
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| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_dce.c | 80 if (src && is_tex_or_prefetch(src) && (src->regs[0]->wrmask > 1)) { in remove_unused_by_block()
81 src->regs[0]->wrmask &= ~(1 << instr->split.off); in remove_unused_by_block()
175 instr->regs[1]->wrmask = src->regs[0]->wrmask; in find_and_remove_unused()
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| D | ir3_a6xx.c | 52 ldib->regs[0]->wrmask = MASK(intr->num_components); in emit_intrinsic_load_ssbo()
69 unsigned wrmask = nir_intrinsic_write_mask(intr); in emit_intrinsic_store_ssbo() local
70 unsigned ncomp = ffs(~wrmask) - 1; in emit_intrinsic_store_ssbo()
72 assert(wrmask == BITFIELD_MASK(intr->num_components)); in emit_intrinsic_store_ssbo()
209 ldib->regs[0]->wrmask = MASK(intr->num_components); in emit_intrinsic_load_image()
356 resinfo->regs[0]->wrmask = MASK(3); in emit_intrinsic_image_size()
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| D | ir3_a4xx.c | 59 ldgb->regs[0]->wrmask = MASK(intr->num_components); in emit_intrinsic_load_ssbo()
75 unsigned wrmask = nir_intrinsic_write_mask(intr); in emit_intrinsic_store_ssbo() local
76 unsigned ncomp = ffs(~wrmask) - 1; in emit_intrinsic_store_ssbo()
78 assert(wrmask == BITFIELD_MASK(intr->num_components)); in emit_intrinsic_store_ssbo()
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| D | ir3_shader.c | 108 unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1; in fixup_regfootprint()
550 if (reg->wrmask > 0x1) in ir3_shader_disasm()
551 fprintf(out, " (wrmask=0x%x)", reg->wrmask); in ir3_shader_disasm()
562 fetch->wrmask, fetch->cmd); in ir3_shader_disasm()
571 if (reg->wrmask > 0x1) in ir3_shader_disasm()
572 fprintf(out, " (wrmask=0x%x)", reg->wrmask); in ir3_shader_disasm()
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| D | ir3_validate.c | 71 validate_assert(ctx, src->regs[0]->wrmask == reg->wrmask); in validate_src()
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| D | ir3_print.c | 212 if (reg->wrmask > 0x1) in print_reg_name()
213 printf(" (wrmask=0x%x)", reg->wrmask); in print_reg_name()
235 if (instr->regs[0]->wrmask & (1 << i)) in print_instr()
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| D | ir3.h | 118 unsigned wrmask : 16; /* up to vec16 */ member
906 return util_last_bit(instr->regs[0]->wrmask); in dest_regs()
1361 reg->wrmask = src->regs[0]->wrmask; in __ssa_src()
1661 unsigned wrmask, unsigned flags, struct ir3_instruction *samp_tex, in INSTR0()
1668 __ssa_dst(sam)->wrmask = wrmask; in INSTR0()
1755 for (unsigned mask = reg->wrmask, n = reg->num; mask; mask >>= 1, n++) in regmask_set()
1770 for (unsigned mask = reg->wrmask, n = reg->num; mask; mask >>= 1, n++) in regmask_get()
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| D | ir3_compiler_nir.c | 60 __ssa_dst(in)->wrmask = compmask; in create_input()
83 instr->regs[2]->wrmask = 0x3; in create_frag_input()
266 unsigned dst_sz, wrmask; in emit_alu() local
272 wrmask = (1 << dst_sz) - 1; in emit_alu()
275 wrmask = alu->dest.write_mask; in emit_alu()
312 if (wrmask & (1 << i)) { in emit_alu()
736 ldc->regs[0]->wrmask = MASK(ncomp); in emit_intrinsic_load_ubo_ldc()
840 resinfo->regs[0]->wrmask = MASK(3); in emit_intrinsic_ssbo_size()
881 ldl->regs[0]->wrmask = MASK(intr->num_components); in emit_intrinsic_load_shared()
896 unsigned base, wrmask, ncomp; in emit_intrinsic_store_shared() local
[all …]
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| D | ir3_context.c | 349 collect->regs[0]->wrmask = MASK(arrsz); in ir3_create_collect()
363 if ((n == 1) && (src->regs[0]->wrmask == 0x1) && in ir3_split_dest()
398 if (src->regs[0]->wrmask & (1 << (i + base))) in ir3_split_dest()
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| D | ir3_ra.c | 217 *sz = util_last_bit(instr->regs[0]->wrmask); in get_definer()
727 int writemask_skipped_regs = ffs(instr->regs[0]->wrmask) - 1; in ra_block_compute_live_ranges()
1158 unsigned n = ffs(id->defn->regs[0]->wrmask); in reg_assign()
1188 (util_bitcount(instr->regs[1]->wrmask) > 1)) in should_assign()
1191 (util_bitcount(instr->regs[0]->wrmask) > 1)) in should_assign()
1431 !(instr->regs[0]->wrmask & (1 << i))) in precolor()
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| D | ir3_parser.y | 74 unsigned wrmask; member
144 reg->wrmask = MAX2(1, rflags.wrmask); in new_reg()
145 rflags.flags = rflags.wrmask = 0; in new_reg()
838 | T_WRMASK { rflags.wrmask = $1; }
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| D | ir3_postsched.c | 421 foreach_bit (b, reg->wrmask) { in calculate_deps()
453 foreach_bit (b, reg->wrmask) { in calculate_deps()
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| D | ir3_ra.h | 316 !(instr->regs[0]->wrmask & (1 << i))) in __ra_init_def_itr()
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| D | ir3.c | 105 components = util_last_bit(reg->wrmask); in reg()
521 cat5->wrmask = dst->wrmask; in emit_cat5()
1009 reg->wrmask = 1; in reg_create()
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| D | ir3_shader.h | 263 uint8_t wrmask; member
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| D | instr-a3xx.h | 716 uint32_t wrmask : 4; /* write-mask */ member
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| /external/mesa3d/src/compiler/nir/tests/ |
| D | load_store_vectorizer_tests.cpp | 56 unsigned wrmask=0xf, unsigned access=0);
62 uint32_t id, unsigned bit_size=32, unsigned components=1, unsigned wrmask=0xf,
68 unsigned bit_size=32, unsigned components=1, unsigned wrmask=0xf);
259 unsigned bit_size, unsigned components, unsigned wrmask, unsigned access) in create_indirect_store() argument
292 nir_intrinsic_set_write_mask(store, wrmask & ((1 << components) - 1)); in create_indirect_store()
307 unsigned bit_size, unsigned components, unsigned wrmask, unsigned access) in create_store() argument
309 …create_indirect_store(mode, binding, nir_imm_int(b, offset), id, bit_size, components, wrmask, acc… in create_store()
327 unsigned bit_size, unsigned components, unsigned wrmask) in create_shared_store() argument
339 nir_intrinsic_set_write_mask(store, wrmask & ((1 << components) - 1)); in create_shared_store()
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_tgsi_lower_yuv.c | 63 const struct tgsi_full_dst_register *orig_dst, unsigned wrmask) in reg_dst() argument
66 dst->Register.WriteMask &= wrmask; in reg_dst()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_shader_info.c | 54 widen_writemask(uint32_t wrmask) in widen_writemask() argument
58 new_wrmask |= (wrmask & (1 << i) ? 0x3 : 0x0) << (i * 2); in widen_writemask()
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