1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This header is BSD licensed so anyone can use the definitions 11 * to implement compatible drivers/servers: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. Neither the name of IBM nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 */ 37 38 #ifndef VIRTIO_GPU_HW_H 39 #define VIRTIO_GPU_HW_H 40 41 #include "linux_types.h" 42 43 #define VIRTIO_GPU_F_VIRGL 0 44 #define VIRTIO_GPU_F_RESOURCE_BLOB 3 45 46 enum virtio_gpu_ctrl_type { 47 VIRTIO_GPU_UNDEFINED = 0, 48 49 /* 2d commands */ 50 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 51 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 52 VIRTIO_GPU_CMD_RESOURCE_UNREF, 53 VIRTIO_GPU_CMD_SET_SCANOUT, 54 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 55 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 56 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 57 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 58 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 59 VIRTIO_GPU_CMD_GET_CAPSET, 60 VIRTIO_GPU_CMD_GET_EDID, 61 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID, 62 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB, 63 64 /* 3d commands */ 65 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 66 VIRTIO_GPU_CMD_CTX_DESTROY, 67 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 68 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 69 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 70 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 71 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 72 VIRTIO_GPU_CMD_SUBMIT_3D, 73 VIRTIO_GPU_CMD_RESOURCE_MAP, 74 VIRTIO_GPU_CMD_RESOURCE_UNMAP, 75 76 /* cursor commands */ 77 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 78 VIRTIO_GPU_CMD_MOVE_CURSOR, 79 80 /* success responses */ 81 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 82 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 83 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 84 VIRTIO_GPU_RESP_OK_CAPSET, 85 VIRTIO_GPU_RESP_OK_EDID, 86 VIRTIO_GPU_RESP_OK_RESOURCE_UUID, 87 VIRTIO_GPU_RESP_OK_MAP_INFO, 88 89 /* error responses */ 90 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 91 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 92 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 93 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 94 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 95 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 96 }; 97 98 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 99 100 struct virtio_gpu_ctrl_hdr { 101 uint32_t type; 102 uint32_t flags; 103 uint64_t fence_id; 104 uint32_t ctx_id; 105 uint32_t padding; 106 }; 107 108 /* data passed in the cursor vq */ 109 110 struct virtio_gpu_cursor_pos { 111 uint32_t scanout_id; 112 uint32_t x; 113 uint32_t y; 114 uint32_t padding; 115 }; 116 117 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */ 118 struct virtio_gpu_update_cursor { 119 struct virtio_gpu_ctrl_hdr hdr; 120 struct virtio_gpu_cursor_pos pos; /* update & move */ 121 uint32_t resource_id; /* update only */ 122 uint32_t hot_x; /* update only */ 123 uint32_t hot_y; /* update only */ 124 uint32_t padding; 125 }; 126 127 /* data passed in the control vq, 2d related */ 128 129 struct virtio_gpu_rect { 130 uint32_t x; 131 uint32_t y; 132 uint32_t width; 133 uint32_t height; 134 }; 135 136 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */ 137 struct virtio_gpu_resource_unref { 138 struct virtio_gpu_ctrl_hdr hdr; 139 uint32_t resource_id; 140 uint32_t padding; 141 }; 142 143 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */ 144 struct virtio_gpu_resource_create_2d { 145 struct virtio_gpu_ctrl_hdr hdr; 146 uint32_t resource_id; 147 uint32_t format; 148 uint32_t width; 149 uint32_t height; 150 }; 151 152 /* VIRTIO_GPU_CMD_SET_SCANOUT */ 153 struct virtio_gpu_set_scanout { 154 struct virtio_gpu_ctrl_hdr hdr; 155 struct virtio_gpu_rect r; 156 uint32_t scanout_id; 157 uint32_t resource_id; 158 }; 159 160 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */ 161 struct virtio_gpu_resource_flush { 162 struct virtio_gpu_ctrl_hdr hdr; 163 struct virtio_gpu_rect r; 164 uint32_t resource_id; 165 uint32_t padding; 166 }; 167 168 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */ 169 struct virtio_gpu_transfer_to_host_2d { 170 struct virtio_gpu_ctrl_hdr hdr; 171 struct virtio_gpu_rect r; 172 uint64_t offset; 173 uint32_t resource_id; 174 uint32_t padding; 175 }; 176 177 struct virtio_gpu_mem_entry { 178 uint64_t addr; 179 uint32_t length; 180 uint32_t padding; 181 }; 182 183 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */ 184 struct virtio_gpu_resource_attach_backing { 185 struct virtio_gpu_ctrl_hdr hdr; 186 uint32_t resource_id; 187 uint32_t nr_entries; 188 }; 189 190 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */ 191 struct virtio_gpu_resource_detach_backing { 192 struct virtio_gpu_ctrl_hdr hdr; 193 uint32_t resource_id; 194 uint32_t padding; 195 }; 196 197 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */ 198 #define VIRTIO_GPU_MAX_SCANOUTS 16 199 struct virtio_gpu_resp_display_info { 200 struct virtio_gpu_ctrl_hdr hdr; 201 struct virtio_gpu_display_one { 202 struct virtio_gpu_rect r; 203 uint32_t enabled; 204 uint32_t flags; 205 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 206 }; 207 208 /* data passed in the control vq, 3d related */ 209 210 struct virtio_gpu_box { 211 uint32_t x, y, z; 212 uint32_t w, h, d; 213 }; 214 215 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */ 216 struct virtio_gpu_transfer_host_3d { 217 struct virtio_gpu_ctrl_hdr hdr; 218 struct virtio_gpu_box box; 219 uint64_t offset; 220 uint32_t resource_id; 221 uint32_t level; 222 uint32_t stride; 223 uint32_t layer_stride; 224 }; 225 226 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */ 227 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 228 struct virtio_gpu_resource_create_3d { 229 struct virtio_gpu_ctrl_hdr hdr; 230 uint32_t resource_id; 231 uint32_t target; 232 uint32_t format; 233 uint32_t bind; 234 uint32_t width; 235 uint32_t height; 236 uint32_t depth; 237 uint32_t array_size; 238 uint32_t last_level; 239 uint32_t nr_samples; 240 uint32_t flags; 241 uint32_t padding; 242 }; 243 244 /* VIRTIO_GPU_CMD_CTX_CREATE */ 245 struct virtio_gpu_ctx_create { 246 struct virtio_gpu_ctrl_hdr hdr; 247 uint32_t nlen; 248 uint32_t padding; 249 char debug_name[64]; 250 }; 251 252 /* VIRTIO_GPU_CMD_CTX_DESTROY */ 253 struct virtio_gpu_ctx_destroy { 254 struct virtio_gpu_ctrl_hdr hdr; 255 }; 256 257 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */ 258 struct virtio_gpu_ctx_resource { 259 struct virtio_gpu_ctrl_hdr hdr; 260 uint32_t resource_id; 261 uint32_t padding; 262 }; 263 264 /* VIRTIO_GPU_CMD_SUBMIT_3D */ 265 struct virtio_gpu_cmd_submit { 266 struct virtio_gpu_ctrl_hdr hdr; 267 uint32_t size; 268 uint32_t padding; 269 }; 270 271 #define VIRTIO_GPU_CAPSET_VIRGL 1 272 #define VIRTIO_GPU_CAPSET_VIRGL2 2 273 274 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ 275 struct virtio_gpu_get_capset_info { 276 struct virtio_gpu_ctrl_hdr hdr; 277 uint32_t capset_index; 278 uint32_t padding; 279 }; 280 281 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */ 282 struct virtio_gpu_resp_capset_info { 283 struct virtio_gpu_ctrl_hdr hdr; 284 uint32_t capset_id; 285 uint32_t capset_max_version; 286 uint32_t capset_max_size; 287 uint32_t padding; 288 }; 289 290 /* VIRTIO_GPU_CMD_GET_CAPSET */ 291 struct virtio_gpu_get_capset { 292 struct virtio_gpu_ctrl_hdr hdr; 293 uint32_t capset_id; 294 uint32_t capset_version; 295 }; 296 297 /* VIRTIO_GPU_RESP_OK_CAPSET */ 298 struct virtio_gpu_resp_capset { 299 struct virtio_gpu_ctrl_hdr hdr; 300 uint8_t capset_data[]; 301 }; 302 303 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */ 304 struct virtio_gpu_resource_create_blob { 305 struct virtio_gpu_ctrl_hdr hdr; 306 uint32_t resource_id; 307 #define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001 308 #define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002 309 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003 310 311 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001 312 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002 313 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004 314 /* zero is invalid blob mem */ 315 uint32_t blob_mem; 316 uint32_t blob_flags; 317 uint32_t nr_entries; 318 uint64_t blob_id; 319 uint64_t size; 320 /* 321 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow 322 */ 323 }; 324 325 /* VIRTIO_GPU_CMD_RESOURCE_MAP */ 326 struct virtio_gpu_resource_map { 327 struct virtio_gpu_ctrl_hdr hdr; 328 uint32_t resource_id; 329 uint32_t padding; 330 uint64_t offset; 331 }; 332 333 /* VIRTIO_GPU_RESP_OK_MAP_INFO */ 334 #define VIRTIO_GPU_MAP_CACHE_MASK 0x0f 335 #define VIRTIO_GPU_MAP_CACHE_NONE 0x00 336 #define VIRTIO_GPU_MAP_CACHE_CACHED 0x01 337 #define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02 338 #define VIRTIO_GPU_MAP_CACHE_WC 0x03 339 struct virtio_gpu_resp_map_info { 340 struct virtio_gpu_ctrl_hdr hdr; 341 uint32_t map_flags; 342 uint32_t padding; 343 }; 344 345 /* VIRTIO_GPU_CMD_RESOURCE_UNMAP */ 346 struct virtio_gpu_resource_unmap { 347 struct virtio_gpu_ctrl_hdr hdr; 348 uint32_t resource_id; 349 uint32_t padding; 350 }; 351 352 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 353 354 struct virtio_gpu_config { 355 uint32_t events_read; 356 uint32_t events_clear; 357 uint32_t num_scanouts; 358 uint32_t num_capsets; 359 }; 360 361 /* simple formats for fbcon/X use */ 362 enum virtio_gpu_formats { 363 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 364 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 365 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 366 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 367 368 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 369 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 370 371 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 372 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 373 }; 374 375 #endif 376