1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #ifndef __MSM_DRM_H__ 26 #define __MSM_DRM_H__ 27 28 #include "drm.h" 29 #include "sde_drm.h" 30 31 #if defined(__cplusplus) 32 extern "C" { 33 #endif 34 35 /* Please note that modifications to all structs defined here are 36 * subject to backwards-compatibility constraints: 37 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit 38 * user/kernel compatibility 39 * 2) Keep fields aligned to their size 40 * 3) Because of how drm_ioctl() works, we can add new fields at 41 * the end of an ioctl if some care is taken: drm_ioctl() will 42 * zero out the new fields at the tail of the ioctl, so a zero 43 * value should have a backwards compatible meaning. And for 44 * output params, userspace won't see the newly added output 45 * fields.. so that has to be somehow ok. 46 */ 47 48 #define MSM_PIPE_NONE 0x00 49 #define MSM_PIPE_2D0 0x01 50 #define MSM_PIPE_2D1 0x02 51 #define MSM_PIPE_3D0 0x10 52 53 /* The pipe-id just uses the lower bits, so can be OR'd with flags in 54 * the upper 16 bits (which could be extended further, if needed, maybe 55 * we extend/overload the pipe-id some day to deal with multiple rings, 56 * but even then I don't think we need the full lower 16 bits). 57 */ 58 #define MSM_PIPE_ID_MASK 0xffff 59 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 60 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 61 62 /* timeouts are specified in clock-monotonic absolute times (to simplify 63 * restarting interrupted ioctls). The following struct is logically the 64 * same as 'struct timespec' but 32/64b ABI safe. 65 */ 66 struct drm_msm_timespec { 67 __s64 tv_sec; /* seconds */ 68 __s64 tv_nsec; /* nanoseconds */ 69 }; 70 71 /* 72 * Colorimetry Data Block values 73 * These bit nums are defined as per the CTA spec 74 * and indicate the colorspaces supported by the sink 75 */ 76 #define DRM_EDID_CLRMETRY_xvYCC_601 (1 << 0) 77 #define DRM_EDID_CLRMETRY_xvYCC_709 (1 << 1) 78 #define DRM_EDID_CLRMETRY_sYCC_601 (1 << 2) 79 #define DRM_EDID_CLRMETRY_ADOBE_YCC_601 (1 << 3) 80 #define DRM_EDID_CLRMETRY_ADOBE_RGB (1 << 4) 81 #define DRM_EDID_CLRMETRY_BT2020_CYCC (1 << 5) 82 #define DRM_EDID_CLRMETRY_BT2020_YCC (1 << 6) 83 #define DRM_EDID_CLRMETRY_BT2020_RGB (1 << 7) 84 #define DRM_EDID_CLRMETRY_DCI_P3 (1 << 15) 85 86 /* 87 * HDR Metadata 88 * These are defined as per EDID spec and shall be used by the sink 89 * to set the HDR metadata for playback from userspace. 90 */ 91 92 #define HDR_PRIMARIES_COUNT 3 93 94 /* HDR EOTF */ 95 #define HDR_EOTF_SDR_LUM_RANGE 0x0 96 #define HDR_EOTF_HDR_LUM_RANGE 0x1 97 #define HDR_EOTF_SMTPE_ST2084 0x2 98 #define HDR_EOTF_HLG 0x3 99 100 #define DRM_MSM_EXT_HDR_METADATA 101 #define DRM_MSM_EXT_HDR_PLUS_METADATA 102 struct drm_msm_ext_hdr_metadata { 103 __u32 hdr_state; /* HDR state */ 104 __u32 eotf; /* electro optical transfer function */ 105 __u32 hdr_supported; /* HDR supported */ 106 __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; /* Primaries x */ 107 __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; /* Primaries y */ 108 __u32 white_point_x; /* white_point_x */ 109 __u32 white_point_y; /* white_point_y */ 110 __u32 max_luminance; /* Max luminance */ 111 __u32 min_luminance; /* Min Luminance */ 112 __u32 max_content_light_level; /* max content light level */ 113 __u32 max_average_light_level; /* max average light level */ 114 115 __u64 hdr_plus_payload; /* user pointer to dynamic HDR payload */ 116 __u32 hdr_plus_payload_size;/* size of dynamic HDR payload data */ 117 }; 118 119 /** 120 * HDR sink properties 121 * These are defined as per EDID spec and shall be used by the userspace 122 * to determine the HDR properties to be set to the sink. 123 */ 124 #define DRM_MSM_EXT_HDR_PROPERTIES 125 #define DRM_MSM_EXT_HDR_PLUS_PROPERTIES 126 struct drm_msm_ext_hdr_properties { 127 __u8 hdr_metadata_type_one; /* static metadata type one */ 128 __u32 hdr_supported; /* HDR supported */ 129 __u32 hdr_eotf; /* electro optical transfer function */ 130 __u32 hdr_max_luminance; /* Max luminance */ 131 __u32 hdr_avg_luminance; /* Avg luminance */ 132 __u32 hdr_min_luminance; /* Min Luminance */ 133 134 __u32 hdr_plus_supported; /* HDR10+ supported */ 135 }; 136 137 #define MSM_PARAM_GPU_ID 0x01 138 #define MSM_PARAM_GMEM_SIZE 0x02 139 #define MSM_PARAM_CHIP_ID 0x03 140 #define MSM_PARAM_MAX_FREQ 0x04 141 #define MSM_PARAM_TIMESTAMP 0x05 142 #define MSM_PARAM_GMEM_BASE 0x06 143 #define MSM_PARAM_NR_RINGS 0x07 144 145 struct drm_msm_param { 146 __u32 pipe; /* in, MSM_PIPE_x */ 147 __u32 param; /* in, MSM_PARAM_x */ 148 __u64 value; /* out (get_param) or in (set_param) */ 149 }; 150 151 /* 152 * GEM buffers: 153 */ 154 155 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ 156 #define MSM_BO_GPU_READONLY 0x00000002 157 #define MSM_BO_CACHE_MASK 0x000f0000 158 /* cache modes */ 159 #define MSM_BO_CACHED 0x00010000 160 #define MSM_BO_WC 0x00020000 161 #define MSM_BO_UNCACHED 0x00040000 162 163 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 164 MSM_BO_GPU_READONLY | \ 165 MSM_BO_CACHED | \ 166 MSM_BO_WC | \ 167 MSM_BO_UNCACHED) 168 169 struct drm_msm_gem_new { 170 __u64 size; /* in */ 171 __u32 flags; /* in, mask of MSM_BO_x */ 172 __u32 handle; /* out */ 173 }; 174 175 #define MSM_INFO_IOVA 0x01 176 177 #define MSM_INFO_FLAGS (MSM_INFO_IOVA) 178 179 struct drm_msm_gem_info { 180 __u32 handle; /* in */ 181 __u32 flags; /* in - combination of MSM_INFO_* flags */ 182 __u64 offset; /* out, mmap() offset or iova */ 183 }; 184 185 #define MSM_PREP_READ 0x01 186 #define MSM_PREP_WRITE 0x02 187 #define MSM_PREP_NOSYNC 0x04 188 189 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 190 191 struct drm_msm_gem_cpu_prep { 192 __u32 handle; /* in */ 193 __u32 op; /* in, mask of MSM_PREP_x */ 194 struct drm_msm_timespec timeout; /* in */ 195 }; 196 197 struct drm_msm_gem_cpu_fini { 198 __u32 handle; /* in */ 199 }; 200 201 /* 202 * Cmdstream Submission: 203 */ 204 205 /* The value written into the cmdstream is logically: 206 * 207 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or 208 * 209 * When we have GPU's w/ >32bit ptrs, it should be possible to deal 210 * with this by emit'ing two reloc entries with appropriate shift 211 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. 212 * 213 * NOTE that reloc's must be sorted by order of increasing submit_offset, 214 * otherwise EINVAL. 215 */ 216 struct drm_msm_gem_submit_reloc { 217 __u32 submit_offset; /* in, offset from submit_bo */ 218 #ifdef __cplusplus 219 __u32 or_val; 220 #else 221 __u32 or; /* in, value OR'd with result */ 222 #endif 223 __s32 shift; /* in, amount of left shift (can be negative) */ 224 __u32 reloc_idx; /* in, index of reloc_bo buffer */ 225 __u64 reloc_offset; /* in, offset from start of reloc_bo */ 226 }; 227 228 /* submit-types: 229 * BUF - this cmd buffer is executed normally. 230 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are 231 * processed normally, but the kernel does not setup an IB to 232 * this buffer in the first-level ringbuffer 233 * CTX_RESTORE_BUF - only executed if there has been a GPU context 234 * switch since the last SUBMIT ioctl 235 */ 236 #define MSM_SUBMIT_CMD_BUF 0x0001 237 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 238 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 239 struct drm_msm_gem_submit_cmd { 240 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ 241 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ 242 __u32 submit_offset; /* in, offset into submit_bo */ 243 __u32 size; /* in, cmdstream size */ 244 __u32 pad; 245 __u32 nr_relocs; /* in, number of submit_reloc's */ 246 __u64 relocs; /* in, ptr to array of submit_reloc's */ 247 }; 248 249 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the 250 * cmdstream buffer(s) themselves or reloc entries) has one (and only 251 * one) entry in the submit->bos[] table. 252 * 253 * As a optimization, the current buffer (gpu virtual address) can be 254 * passed back through the 'presumed' field. If on a subsequent reloc, 255 * userspace passes back a 'presumed' address that is still valid, 256 * then patching the cmdstream for this entry is skipped. This can 257 * avoid kernel needing to map/access the cmdstream bo in the common 258 * case. 259 */ 260 #define MSM_SUBMIT_BO_READ 0x0001 261 #define MSM_SUBMIT_BO_WRITE 0x0002 262 263 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 264 265 struct drm_msm_gem_submit_bo { 266 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ 267 __u32 handle; /* in, GEM handle */ 268 __u64 presumed; /* in/out, presumed buffer address */ 269 }; 270 271 /* Valid submit ioctl flags: */ 272 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ 273 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ 274 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ 275 #define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */ 276 #define MSM_SUBMIT_FLAGS ( \ 277 MSM_SUBMIT_NO_IMPLICIT | \ 278 MSM_SUBMIT_FENCE_FD_IN | \ 279 MSM_SUBMIT_FENCE_FD_OUT | \ 280 MSM_SUBMIT_SUDO | \ 281 0) 282 283 /* Each cmdstream submit consists of a table of buffers involved, and 284 * one or more cmdstream buffers. This allows for conditional execution 285 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 286 */ 287 struct drm_msm_gem_submit { 288 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ 289 __u32 fence; /* out */ 290 __u32 nr_bos; /* in, number of submit_bo's */ 291 __u32 nr_cmds; /* in, number of submit_cmd's */ 292 __u64 bos; /* in, ptr to array of submit_bo's */ 293 __u64 cmds; /* in, ptr to array of submit_cmd's */ 294 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ 295 __u32 queueid; /* in, submitqueue id */ 296 }; 297 298 /* The normal way to synchronize with the GPU is just to CPU_PREP on 299 * a buffer if you need to access it from the CPU (other cmdstream 300 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 301 * handle the required synchronization under the hood). This ioctl 302 * mainly just exists as a way to implement the gallium pipe_fence 303 * APIs without requiring a dummy bo to synchronize on. 304 */ 305 struct drm_msm_wait_fence { 306 __u32 fence; /* in */ 307 __u32 pad; 308 struct drm_msm_timespec timeout; /* in */ 309 __u32 queueid; /* in, submitqueue id */ 310 }; 311 312 /* madvise provides a way to tell the kernel in case a buffers contents 313 * can be discarded under memory pressure, which is useful for userspace 314 * bo cache where we want to optimistically hold on to buffer allocate 315 * and potential mmap, but allow the pages to be discarded under memory 316 * pressure. 317 * 318 * Typical usage would involve madvise(DONTNEED) when buffer enters BO 319 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. 320 * In the WILLNEED case, 'retained' indicates to userspace whether the 321 * backing pages still exist. 322 */ 323 #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ 324 #define MSM_MADV_DONTNEED 1 /* backing pages not needed */ 325 #define __MSM_MADV_PURGED 2 /* internal state */ 326 327 struct drm_msm_gem_madvise { 328 __u32 handle; /* in, GEM handle */ 329 __u32 madv; /* in, MSM_MADV_x */ 330 __u32 retained; /* out, whether backing store still exists */ 331 }; 332 333 /* HDR WRGB x and y index */ 334 #define DISPLAY_PRIMARIES_WX 0 335 #define DISPLAY_PRIMARIES_WY 1 336 #define DISPLAY_PRIMARIES_RX 2 337 #define DISPLAY_PRIMARIES_RY 3 338 #define DISPLAY_PRIMARIES_GX 4 339 #define DISPLAY_PRIMARIES_GY 5 340 #define DISPLAY_PRIMARIES_BX 6 341 #define DISPLAY_PRIMARIES_BY 7 342 #define DISPLAY_PRIMARIES_MAX 8 343 344 struct drm_panel_hdr_properties { 345 __u32 hdr_enabled; 346 347 /* WRGB X and y values arrayed in format */ 348 /* [WX, WY, RX, RY, GX, GY, BX, BY] */ 349 __u32 display_primaries[DISPLAY_PRIMARIES_MAX]; 350 351 /* peak brightness supported by panel */ 352 __u32 peak_brightness; 353 /* Blackness level supported by panel */ 354 __u32 blackness_level; 355 }; 356 357 /** 358 * struct drm_msm_event_req - Payload to event enable/disable ioctls. 359 * @object_id: DRM object id. e.g.: for crtc pass crtc id. 360 * @object_type: DRM object type. e.g.: for crtc set it to DRM_MODE_OBJECT_CRTC. 361 * @event: Event for which notification is being enabled/disabled. 362 * e.g.: for Histogram set - DRM_EVENT_HISTOGRAM. 363 * @client_context: Opaque pointer that will be returned during event response 364 * notification. 365 * @index: Object index(e.g.: crtc index), optional for user-space to set. 366 * Driver will override value based on object_id and object_type. 367 */ 368 struct drm_msm_event_req { 369 __u32 object_id; 370 __u32 object_type; 371 __u32 event; 372 __u64 client_context; 373 __u32 index; 374 }; 375 376 /** 377 * struct drm_msm_event_resp - payload returned when read is called for 378 * custom notifications. 379 * @base: Event type and length of complete notification payload. 380 * @info: Contains information about DRM that which raised this event. 381 * @data: Custom payload that driver returns for event type. 382 * size of data = base.length - (sizeof(base) + sizeof(info)) 383 */ 384 struct drm_msm_event_resp { 385 struct drm_event base; 386 struct drm_msm_event_req info; 387 __u8 data[]; 388 }; 389 390 /* 391 * Draw queues allow the user to set specific submission parameter. Command 392 * submissions specify a specific submitqueue to use. ID 0 is reserved for 393 * backwards compatibility as a "default" submitqueue 394 */ 395 396 #define MSM_SUBMITQUEUE_FLAGS (0) 397 398 struct drm_msm_submitqueue { 399 __u32 flags; /* in, MSM_SUBMITQUEUE_x */ 400 __u32 prio; /* in, Priority level */ 401 __u32 id; /* out, identifier */ 402 }; 403 404 /** 405 * struct drm_msm_power_ctrl: Payload to enable/disable the power vote 406 * @enable: enable/disable the power vote 407 * @flags: operation control flags, for future use 408 */ 409 struct drm_msm_power_ctrl { 410 __u32 enable; 411 __u32 flags; 412 }; 413 414 #define DRM_MSM_GET_PARAM 0x00 415 /* placeholder: 416 #define DRM_MSM_SET_PARAM 0x01 417 */ 418 #define DRM_MSM_GEM_NEW 0x02 419 #define DRM_MSM_GEM_INFO 0x03 420 #define DRM_MSM_GEM_CPU_PREP 0x04 421 #define DRM_MSM_GEM_CPU_FINI 0x05 422 #define DRM_MSM_GEM_SUBMIT 0x06 423 #define DRM_MSM_WAIT_FENCE 0x07 424 #define DRM_MSM_GEM_MADVISE 0x08 425 /* placeholder: 426 #define DRM_MSM_GEM_SVM_NEW 0x09 427 */ 428 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 429 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 430 #define DRM_SDE_WB_CONFIG 0x40 431 #define DRM_MSM_REGISTER_EVENT 0x41 432 #define DRM_MSM_DEREGISTER_EVENT 0x42 433 #define DRM_MSM_RMFB2 0x43 434 #define DRM_MSM_POWER_CTRL 0x44 435 436 /* sde custom events */ 437 #define DRM_EVENT_HISTOGRAM 0x80000000 438 #define DRM_EVENT_AD_BACKLIGHT 0x80000001 439 #define DRM_EVENT_CRTC_POWER 0x80000002 440 #define DRM_EVENT_SYS_BACKLIGHT 0x80000003 441 #define DRM_EVENT_SDE_POWER 0x80000004 442 #define DRM_EVENT_IDLE_NOTIFY 0x80000005 443 #define DRM_EVENT_PANEL_DEAD 0x80000006 /* ESD event */ 444 #define DRM_EVENT_SDE_HW_RECOVERY 0X80000007 445 #define DRM_EVENT_LTM_HIST 0X80000008 446 #define DRM_EVENT_LTM_WB_PB 0X80000009 447 #define DRM_EVENT_LTM_OFF 0X8000000A 448 449 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 450 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 451 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 452 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 453 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 454 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 455 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 456 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 457 #define DRM_IOCTL_SDE_WB_CONFIG \ 458 DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) 459 #define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ 460 DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) 461 #define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ 462 DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) 463 #define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + \ 464 DRM_MSM_RMFB2), unsigned int) 465 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 466 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 467 #define DRM_IOCTL_MSM_POWER_CTRL DRM_IOW((DRM_COMMAND_BASE + \ 468 DRM_MSM_POWER_CTRL), struct drm_msm_power_ctrl) 469 470 #if defined(__cplusplus) 471 } 472 #endif 473 474 #endif /* __MSM_DRM_H__ */ 475