1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _MSM_NPU_H_ 7 #define _MSM_NPU_H_ 8 9 /* ------------------------------------------------------------------------- 10 * Includes 11 * ------------------------------------------------------------------------- 12 */ 13 #include <linux/types.h> 14 15 /* ------------------------------------------------------------------------- 16 * Defines 17 * ------------------------------------------------------------------------- 18 */ 19 #define MSM_NPU_IOCTL_MAGIC 'n' 20 21 /* get npu info */ 22 #define MSM_NPU_GET_INFO \ 23 _IOWR(MSM_NPU_IOCTL_MAGIC, 1, struct msm_npu_get_info_ioctl) 24 25 /* map buf */ 26 #define MSM_NPU_MAP_BUF \ 27 _IOWR(MSM_NPU_IOCTL_MAGIC, 2, struct msm_npu_map_buf_ioctl) 28 29 /* map buf */ 30 #define MSM_NPU_UNMAP_BUF \ 31 _IOWR(MSM_NPU_IOCTL_MAGIC, 3, struct msm_npu_unmap_buf_ioctl) 32 33 /* load network */ 34 #define MSM_NPU_LOAD_NETWORK \ 35 _IOWR(MSM_NPU_IOCTL_MAGIC, 4, struct msm_npu_load_network_ioctl) 36 37 /* unload network */ 38 #define MSM_NPU_UNLOAD_NETWORK \ 39 _IOWR(MSM_NPU_IOCTL_MAGIC, 5, struct msm_npu_unload_network_ioctl) 40 41 /* exec network */ 42 #define MSM_NPU_EXEC_NETWORK \ 43 _IOWR(MSM_NPU_IOCTL_MAGIC, 6, struct msm_npu_exec_network_ioctl) 44 45 /* load network v2 */ 46 #define MSM_NPU_LOAD_NETWORK_V2 \ 47 _IOWR(MSM_NPU_IOCTL_MAGIC, 7, struct msm_npu_load_network_ioctl_v2) 48 49 /* exec network v2 */ 50 #define MSM_NPU_EXEC_NETWORK_V2 \ 51 _IOWR(MSM_NPU_IOCTL_MAGIC, 8, struct msm_npu_exec_network_ioctl_v2) 52 53 /* receive event */ 54 #define MSM_NPU_RECEIVE_EVENT \ 55 _IOR(MSM_NPU_IOCTL_MAGIC, 9, struct msm_npu_event) 56 57 /* set property */ 58 #define MSM_NPU_SET_PROP \ 59 _IOW(MSM_NPU_IOCTL_MAGIC, 10, struct msm_npu_property) 60 61 /* get property */ 62 #define MSM_NPU_GET_PROP \ 63 _IOW(MSM_NPU_IOCTL_MAGIC, 11, struct msm_npu_property) 64 65 #define MSM_NPU_EVENT_TYPE_START 0x10000000 66 #define MSM_NPU_EVENT_TYPE_EXEC_DONE (MSM_NPU_EVENT_TYPE_START + 1) 67 #define MSM_NPU_EVENT_TYPE_EXEC_V2_DONE (MSM_NPU_EVENT_TYPE_START + 2) 68 #define MSM_NPU_EVENT_TYPE_SSR (MSM_NPU_EVENT_TYPE_START + 3) 69 70 #define MSM_NPU_MAX_INPUT_LAYER_NUM 8 71 #define MSM_NPU_MAX_OUTPUT_LAYER_NUM 4 72 #define MSM_NPU_MAX_PATCH_LAYER_NUM (MSM_NPU_MAX_INPUT_LAYER_NUM +\ 73 MSM_NPU_MAX_OUTPUT_LAYER_NUM) 74 75 #define MSM_NPU_PROP_ID_START 0x100 76 #define MSM_NPU_PROP_ID_FW_STATE (MSM_NPU_PROP_ID_START + 0) 77 #define MSM_NPU_PROP_ID_PERF_MODE (MSM_NPU_PROP_ID_START + 1) 78 #define MSM_NPU_PROP_ID_PERF_MODE_MAX (MSM_NPU_PROP_ID_START + 2) 79 #define MSM_NPU_PROP_ID_DRV_VERSION (MSM_NPU_PROP_ID_START + 3) 80 #define MSM_NPU_PROP_ID_HARDWARE_VERSION (MSM_NPU_PROP_ID_START + 4) 81 #define MSM_NPU_PROP_ID_IPC_QUEUE_INFO (MSM_NPU_PROP_ID_START + 5) 82 #define MSM_NPU_PROP_ID_DRV_FEATURE (MSM_NPU_PROP_ID_START + 6) 83 84 #define MSM_NPU_FW_PROP_ID_START 0x1000 85 #define MSM_NPU_PROP_ID_DCVS_MODE (MSM_NPU_FW_PROP_ID_START + 0) 86 #define MSM_NPU_PROP_ID_DCVS_MODE_MAX (MSM_NPU_FW_PROP_ID_START + 1) 87 #define MSM_NPU_PROP_ID_CLK_GATING_MODE (MSM_NPU_FW_PROP_ID_START + 2) 88 #define MSM_NPU_PROP_ID_HW_VERSION (MSM_NPU_FW_PROP_ID_START + 3) 89 #define MSM_NPU_PROP_ID_FW_VERSION (MSM_NPU_FW_PROP_ID_START + 4) 90 #define MSM_NPU_PROP_ID_FW_GETCAPS (MSM_NPU_FW_PROP_ID_START + 5) 91 92 /* features supported by driver */ 93 #define MSM_NPU_FEATURE_MULTI_EXECUTE 0x1 94 #define MSM_NPU_FEATURE_ASYNC_EXECUTE 0x2 95 #define MSM_NPU_FEATURE_DSP_SID_MAPPED 0x8 96 97 #define PROP_PARAM_MAX_SIZE 8 98 99 /* ------------------------------------------------------------------------- 100 * Data Structures 101 * ------------------------------------------------------------------------- 102 */ 103 struct msm_npu_patch_info { 104 /* chunk id */ 105 uint32_t chunk_id; 106 /* instruction size in bytes */ 107 uint16_t instruction_size_in_bytes; 108 /* variable size in bits */ 109 uint16_t variable_size_in_bits; 110 /* shift value in bits */ 111 uint16_t shift_value_in_bits; 112 /* location offset */ 113 uint32_t loc_offset; 114 }; 115 116 struct msm_npu_layer { 117 /* layer id */ 118 uint32_t layer_id; 119 /* patch information*/ 120 struct msm_npu_patch_info patch_info; 121 /* buffer handle */ 122 int32_t buf_hdl; 123 /* buffer size */ 124 uint32_t buf_size; 125 /* physical address */ 126 uint64_t buf_phys_addr; 127 }; 128 129 struct msm_npu_patch_info_v2 { 130 /* patch value */ 131 uint32_t value; 132 /* chunk id */ 133 uint32_t chunk_id; 134 /* instruction size in bytes */ 135 uint32_t instruction_size_in_bytes; 136 /* variable size in bits */ 137 uint32_t variable_size_in_bits; 138 /* shift value in bits */ 139 uint32_t shift_value_in_bits; 140 /* location offset */ 141 uint32_t loc_offset; 142 }; 143 144 struct msm_npu_patch_buf_info { 145 /* physical address to be patched */ 146 uint64_t buf_phys_addr; 147 /* buffer id */ 148 uint32_t buf_id; 149 }; 150 151 /* ------------------------------------------------------------------------- 152 * Data Structures - IOCTLs 153 * ------------------------------------------------------------------------- 154 */ 155 struct msm_npu_map_buf_ioctl { 156 /* buffer ion handle */ 157 int32_t buf_ion_hdl; 158 /* buffer size */ 159 uint32_t size; 160 /* iommu mapped physical address */ 161 uint64_t npu_phys_addr; 162 }; 163 164 struct msm_npu_unmap_buf_ioctl { 165 /* buffer ion handle */ 166 int32_t buf_ion_hdl; 167 /* iommu mapped physical address */ 168 uint64_t npu_phys_addr; 169 }; 170 171 struct msm_npu_get_info_ioctl { 172 /* firmware version */ 173 uint32_t firmware_version; 174 /* reserved */ 175 uint32_t flags; 176 }; 177 178 struct msm_npu_load_network_ioctl { 179 /* buffer ion handle */ 180 int32_t buf_ion_hdl; 181 /* physical address */ 182 uint64_t buf_phys_addr; 183 /* buffer size */ 184 uint32_t buf_size; 185 /* first block size */ 186 uint32_t first_block_size; 187 /* reserved */ 188 uint32_t flags; 189 /* network handle */ 190 uint32_t network_hdl; 191 /* priority */ 192 uint32_t priority; 193 /* perf mode */ 194 uint32_t perf_mode; 195 }; 196 197 struct msm_npu_load_network_ioctl_v2 { 198 /* physical address */ 199 uint64_t buf_phys_addr; 200 /* patch info(v2) for all input/output layers */ 201 uint64_t patch_info; 202 /* buffer ion handle */ 203 int32_t buf_ion_hdl; 204 /* buffer size */ 205 uint32_t buf_size; 206 /* first block size */ 207 uint32_t first_block_size; 208 /* load flags */ 209 uint32_t flags; 210 /* network handle */ 211 uint32_t network_hdl; 212 /* priority */ 213 uint32_t priority; 214 /* perf mode */ 215 uint32_t perf_mode; 216 /* number of layers in the network */ 217 uint32_t num_layers; 218 /* number of layers to be patched */ 219 uint32_t patch_info_num; 220 /* reserved */ 221 uint32_t reserved; 222 }; 223 224 struct msm_npu_unload_network_ioctl { 225 /* network handle */ 226 uint32_t network_hdl; 227 }; 228 229 struct msm_npu_exec_network_ioctl { 230 /* network handle */ 231 uint32_t network_hdl; 232 /* input layer number */ 233 uint32_t input_layer_num; 234 /* input layer info */ 235 struct msm_npu_layer input_layers[MSM_NPU_MAX_INPUT_LAYER_NUM]; 236 /* output layer number */ 237 uint32_t output_layer_num; 238 /* output layer info */ 239 struct msm_npu_layer output_layers[MSM_NPU_MAX_OUTPUT_LAYER_NUM]; 240 /* patching is required */ 241 uint32_t patching_required; 242 /* asynchronous execution */ 243 uint32_t async; 244 /* reserved */ 245 uint32_t flags; 246 }; 247 248 struct msm_npu_exec_network_ioctl_v2 { 249 /* stats buffer to be filled with execution stats */ 250 uint64_t stats_buf_addr; 251 /* patch buf info for both input and output layers */ 252 uint64_t patch_buf_info; 253 /* network handle */ 254 uint32_t network_hdl; 255 /* asynchronous execution */ 256 uint32_t async; 257 /* execution flags */ 258 uint32_t flags; 259 /* stats buf size allocated */ 260 uint32_t stats_buf_size; 261 /* number of layers to be patched */ 262 uint32_t patch_buf_info_num; 263 /* reserved */ 264 uint32_t reserved; 265 }; 266 267 struct msm_npu_event_execute_done { 268 uint32_t network_hdl; 269 int32_t exec_result; 270 }; 271 272 struct msm_npu_event_execute_v2_done { 273 uint32_t network_hdl; 274 int32_t exec_result; 275 /* stats buf size filled */ 276 uint32_t stats_buf_size; 277 }; 278 279 struct msm_npu_event_ssr { 280 uint32_t network_hdl; 281 }; 282 283 struct msm_npu_event { 284 uint32_t type; 285 union { 286 struct msm_npu_event_execute_done exec_done; 287 struct msm_npu_event_execute_v2_done exec_v2_done; 288 struct msm_npu_event_ssr ssr; 289 uint8_t data[128]; 290 } u; 291 uint32_t reserved[4]; 292 }; 293 294 struct msm_npu_property { 295 uint32_t prop_id; 296 uint32_t num_of_params; 297 uint32_t network_hdl; 298 uint32_t prop_param[PROP_PARAM_MAX_SIZE]; 299 }; 300 301 #endif /* _MSM_NPU_H_*/ 302