1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSM_DRM_H__ 20 #define __MSM_DRM_H__ 21 #include "drm.h" 22 #include "sde_drm.h" 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 #define MSM_PIPE_NONE 0x00 27 #define MSM_PIPE_2D0 0x01 28 #define MSM_PIPE_2D1 0x02 29 #define MSM_PIPE_3D0 0x10 30 #define MSM_PIPE_ID_MASK 0xffff 31 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 32 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 33 struct drm_msm_timespec { 34 __s64 tv_sec; 35 __s64 tv_nsec; 36 }; 37 #define DRM_EDID_CLRMETRY_xvYCC_601 (1 << 0) 38 #define DRM_EDID_CLRMETRY_xvYCC_709 (1 << 1) 39 #define DRM_EDID_CLRMETRY_sYCC_601 (1 << 2) 40 #define DRM_EDID_CLRMETRY_ADOBE_YCC_601 (1 << 3) 41 #define DRM_EDID_CLRMETRY_ADOBE_RGB (1 << 4) 42 #define DRM_EDID_CLRMETRY_BT2020_CYCC (1 << 5) 43 #define DRM_EDID_CLRMETRY_BT2020_YCC (1 << 6) 44 #define DRM_EDID_CLRMETRY_BT2020_RGB (1 << 7) 45 #define DRM_EDID_CLRMETRY_DCI_P3 (1 << 15) 46 #define HDR_PRIMARIES_COUNT 3 47 #define HDR_EOTF_SDR_LUM_RANGE 0x0 48 #define HDR_EOTF_HDR_LUM_RANGE 0x1 49 #define HDR_EOTF_SMTPE_ST2084 0x2 50 #define HDR_EOTF_HLG 0x3 51 #define DRM_MSM_EXT_HDR_METADATA 52 #define DRM_MSM_EXT_HDR_PLUS_METADATA 53 struct drm_msm_ext_hdr_metadata { 54 __u32 hdr_state; 55 __u32 eotf; 56 __u32 hdr_supported; 57 __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; 58 __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; 59 __u32 white_point_x; 60 __u32 white_point_y; 61 __u32 max_luminance; 62 __u32 min_luminance; 63 __u32 max_content_light_level; 64 __u32 max_average_light_level; 65 __u64 hdr_plus_payload; 66 __u32 hdr_plus_payload_size; 67 }; 68 #define DRM_MSM_EXT_HDR_PROPERTIES 69 #define DRM_MSM_EXT_HDR_PLUS_PROPERTIES 70 struct drm_msm_ext_hdr_properties { 71 __u8 hdr_metadata_type_one; 72 __u32 hdr_supported; 73 __u32 hdr_eotf; 74 __u32 hdr_max_luminance; 75 __u32 hdr_avg_luminance; 76 __u32 hdr_min_luminance; 77 __u32 hdr_plus_supported; 78 }; 79 #define MSM_PARAM_GPU_ID 0x01 80 #define MSM_PARAM_GMEM_SIZE 0x02 81 #define MSM_PARAM_CHIP_ID 0x03 82 #define MSM_PARAM_MAX_FREQ 0x04 83 #define MSM_PARAM_TIMESTAMP 0x05 84 #define MSM_PARAM_GMEM_BASE 0x06 85 #define MSM_PARAM_NR_RINGS 0x07 86 struct drm_msm_param { 87 __u32 pipe; 88 __u32 param; 89 __u64 value; 90 }; 91 #define MSM_BO_SCANOUT 0x00000001 92 #define MSM_BO_GPU_READONLY 0x00000002 93 #define MSM_BO_CACHE_MASK 0x000f0000 94 #define MSM_BO_CACHED 0x00010000 95 #define MSM_BO_WC 0x00020000 96 #define MSM_BO_UNCACHED 0x00040000 97 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED) 98 struct drm_msm_gem_new { 99 __u64 size; 100 __u32 flags; 101 __u32 handle; 102 }; 103 #define MSM_INFO_IOVA 0x01 104 #define MSM_INFO_FLAGS (MSM_INFO_IOVA) 105 struct drm_msm_gem_info { 106 __u32 handle; 107 __u32 flags; 108 __u64 offset; 109 }; 110 #define MSM_PREP_READ 0x01 111 #define MSM_PREP_WRITE 0x02 112 #define MSM_PREP_NOSYNC 0x04 113 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 114 struct drm_msm_gem_cpu_prep { 115 __u32 handle; 116 __u32 op; 117 struct drm_msm_timespec timeout; 118 }; 119 struct drm_msm_gem_cpu_fini { 120 __u32 handle; 121 }; 122 struct drm_msm_gem_submit_reloc { 123 __u32 submit_offset; 124 #ifdef __cplusplus 125 __u32 or_val; 126 #else 127 __u32 or; 128 #endif 129 __s32 shift; 130 __u32 reloc_idx; 131 __u64 reloc_offset; 132 }; 133 #define MSM_SUBMIT_CMD_BUF 0x0001 134 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 135 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 136 struct drm_msm_gem_submit_cmd { 137 __u32 type; 138 __u32 submit_idx; 139 __u32 submit_offset; 140 __u32 size; 141 __u32 pad; 142 __u32 nr_relocs; 143 __u64 relocs; 144 }; 145 #define MSM_SUBMIT_BO_READ 0x0001 146 #define MSM_SUBMIT_BO_WRITE 0x0002 147 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 148 struct drm_msm_gem_submit_bo { 149 __u32 flags; 150 __u32 handle; 151 __u64 presumed; 152 }; 153 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 154 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 155 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 156 #define MSM_SUBMIT_SUDO 0x10000000 157 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | 0) 158 struct drm_msm_gem_submit { 159 __u32 flags; 160 __u32 fence; 161 __u32 nr_bos; 162 __u32 nr_cmds; 163 __u64 bos; 164 __u64 cmds; 165 __s32 fence_fd; 166 __u32 queueid; 167 }; 168 struct drm_msm_wait_fence { 169 __u32 fence; 170 __u32 pad; 171 struct drm_msm_timespec timeout; 172 __u32 queueid; 173 }; 174 #define MSM_MADV_WILLNEED 0 175 #define MSM_MADV_DONTNEED 1 176 #define __MSM_MADV_PURGED 2 177 struct drm_msm_gem_madvise { 178 __u32 handle; 179 __u32 madv; 180 __u32 retained; 181 }; 182 #define DISPLAY_PRIMARIES_WX 0 183 #define DISPLAY_PRIMARIES_WY 1 184 #define DISPLAY_PRIMARIES_RX 2 185 #define DISPLAY_PRIMARIES_RY 3 186 #define DISPLAY_PRIMARIES_GX 4 187 #define DISPLAY_PRIMARIES_GY 5 188 #define DISPLAY_PRIMARIES_BX 6 189 #define DISPLAY_PRIMARIES_BY 7 190 #define DISPLAY_PRIMARIES_MAX 8 191 struct drm_panel_hdr_properties { 192 __u32 hdr_enabled; 193 __u32 display_primaries[DISPLAY_PRIMARIES_MAX]; 194 __u32 peak_brightness; 195 __u32 blackness_level; 196 }; 197 struct drm_msm_event_req { 198 __u32 object_id; 199 __u32 object_type; 200 __u32 event; 201 __u64 client_context; 202 __u32 index; 203 }; 204 struct drm_msm_event_resp { 205 struct drm_event base; 206 struct drm_msm_event_req info; 207 __u8 data[]; 208 }; 209 #define MSM_SUBMITQUEUE_FLAGS (0) 210 struct drm_msm_submitqueue { 211 __u32 flags; 212 __u32 prio; 213 __u32 id; 214 }; 215 struct drm_msm_power_ctrl { 216 __u32 enable; 217 __u32 flags; 218 }; 219 #define DRM_MSM_GET_PARAM 0x00 220 #define DRM_MSM_GEM_NEW 0x02 221 #define DRM_MSM_GEM_INFO 0x03 222 #define DRM_MSM_GEM_CPU_PREP 0x04 223 #define DRM_MSM_GEM_CPU_FINI 0x05 224 #define DRM_MSM_GEM_SUBMIT 0x06 225 #define DRM_MSM_WAIT_FENCE 0x07 226 #define DRM_MSM_GEM_MADVISE 0x08 227 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 228 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 229 #define DRM_SDE_WB_CONFIG 0x40 230 #define DRM_MSM_REGISTER_EVENT 0x41 231 #define DRM_MSM_DEREGISTER_EVENT 0x42 232 #define DRM_MSM_RMFB2 0x43 233 #define DRM_MSM_POWER_CTRL 0x44 234 #define DRM_EVENT_HISTOGRAM 0x80000000 235 #define DRM_EVENT_AD_BACKLIGHT 0x80000001 236 #define DRM_EVENT_CRTC_POWER 0x80000002 237 #define DRM_EVENT_SYS_BACKLIGHT 0x80000003 238 #define DRM_EVENT_SDE_POWER 0x80000004 239 #define DRM_EVENT_IDLE_NOTIFY 0x80000005 240 #define DRM_EVENT_PANEL_DEAD 0x80000006 241 #define DRM_EVENT_SDE_HW_RECOVERY 0X80000007 242 #define DRM_EVENT_LTM_HIST 0X80000008 243 #define DRM_EVENT_LTM_WB_PB 0X80000009 244 #define DRM_EVENT_LTM_OFF 0X8000000A 245 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 246 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 247 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 248 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 249 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 250 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 251 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 252 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 253 #define DRM_IOCTL_SDE_WB_CONFIG DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) 254 #define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) 255 #define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) 256 #define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_RMFB2), unsigned int) 257 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 258 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 259 #define DRM_IOCTL_MSM_POWER_CTRL DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_POWER_CTRL), struct drm_msm_power_ctrl) 260 #ifdef __cplusplus 261 } 262 #endif 263 #endif 264