1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ 2 /* 3 * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _MSM_MDP_H_ 7 #define _MSM_MDP_H_ 8 9 #include <stdint.h> 10 #include <linux/fb.h> 11 12 #define MSMFB_IOCTL_MAGIC 'm' 13 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 14 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 15 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 16 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 17 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 18 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 19 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 20 /* new ioctls's for set/get ccs matrix */ 21 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 22 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 23 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 24 struct mdp_overlay) 25 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 26 27 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 28 struct msmfb_overlay_data) 29 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 30 31 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 32 struct mdp_page_protection) 33 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 34 struct mdp_page_protection) 35 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 36 struct mdp_overlay) 37 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 38 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 39 struct msmfb_overlay_blt) 40 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 41 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 42 struct mdp_histogram_start_req) 43 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 44 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 45 46 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 47 struct msmfb_overlay_3d) 48 49 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 50 struct msmfb_mixer_info_req) 51 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 52 struct msmfb_overlay_data) 53 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 54 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 55 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 56 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 57 struct msmfb_data) 58 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 59 struct msmfb_data) 60 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 61 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 62 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 63 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 64 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 65 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 66 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 67 struct mdp_display_commit) 68 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 69 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 70 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 71 unsigned int) 72 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 73 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 74 struct mdp_overlay_list) 75 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 76 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \ 77 struct mdp_pp_feature_version) 78 79 #define FB_TYPE_3D_PANEL 0x10101010 80 #define MDP_IMGTYPE2_START 0x10000 81 #define MSMFB_DRIVER_VERSION 0xF9E8D701 82 /* Maximum number of formats supported by MDP*/ 83 #define MDP_IMGTYPE_END 0x100 84 85 /* HW Revisions for different MDSS targets */ 86 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 87 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 88 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 89 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 90 91 #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 92 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 93 94 #define MDSS_MDP_REV(major, minor, step) \ 95 ((((major) & 0x000F) << 28) | \ 96 (((minor) & 0x0FFF) << 16) | \ 97 ((step) & 0xFFFF)) 98 99 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 100 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 101 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 102 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 103 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 104 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 105 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 106 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 107 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ 108 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ 109 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */ 110 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */ 111 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */ 112 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ 113 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ 114 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ 115 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 116 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ 117 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ 118 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) /* msmgold */ 119 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ 120 #define MDSS_MDP_HW_REV_117 MDSS_MDP_REV(1, 17, 0) /* qcs405 */ 121 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msmcobalt */ 122 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msmcobalt v1.0 */ 123 #define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) /* sdm660 */ 124 #define MDSS_MDP_HW_REV_330 MDSS_MDP_REV(3, 3, 0) /* sdm630 */ 125 126 enum { 127 NOTIFY_UPDATE_INIT, 128 NOTIFY_UPDATE_DEINIT, 129 NOTIFY_UPDATE_START, 130 NOTIFY_UPDATE_STOP, 131 NOTIFY_UPDATE_POWER_OFF, 132 }; 133 134 enum { 135 NOTIFY_TYPE_NO_UPDATE, 136 NOTIFY_TYPE_SUSPEND, 137 NOTIFY_TYPE_UPDATE, 138 NOTIFY_TYPE_BL_UPDATE, 139 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 140 }; 141 142 enum { 143 MDP_RGB_565, /* RGB 565 planer */ 144 MDP_XRGB_8888, /* RGB 888 padded */ 145 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 146 MDP_Y_CBCR_H2V2_ADRENO, 147 MDP_ARGB_8888, /* ARGB 888 */ 148 MDP_RGB_888, /* RGB 888 planer */ 149 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 150 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 151 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 152 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 153 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 154 MDP_Y_CRCB_H1V2, 155 MDP_Y_CBCR_H1V2, 156 MDP_RGBA_8888, /* ARGB 888 */ 157 MDP_BGRA_8888, /* ABGR 888 */ 158 MDP_RGBX_8888, /* RGBX 888 */ 159 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 160 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 161 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 162 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 163 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 164 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 165 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 166 MDP_YCRCB_H1V1, /* YCrCb interleave */ 167 MDP_YCBCR_H1V1, /* YCbCr interleave */ 168 MDP_BGR_565, /* BGR 565 planer */ 169 MDP_BGR_888, /* BGR 888 */ 170 MDP_Y_CBCR_H2V2_VENUS, 171 MDP_BGRX_8888, /* BGRX 8888 */ 172 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 173 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 174 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 175 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 176 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 177 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 178 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 179 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 180 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 181 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 182 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 183 MDP_ARGB_1555, /*ARGB 1555*/ 184 MDP_RGBA_5551, /*RGBA 5551*/ 185 MDP_ARGB_4444, /*ARGB 4444*/ 186 MDP_RGBA_4444, /*RGBA 4444*/ 187 MDP_RGB_565_UBWC, 188 MDP_RGBA_8888_UBWC, 189 MDP_Y_CBCR_H2V2_UBWC, 190 MDP_RGBX_8888_UBWC, 191 MDP_Y_CRCB_H2V2_VENUS, 192 MDP_IMGTYPE_LIMIT, 193 MDP_RGB_BORDERFILL, /* border fill pipe */ 194 MDP_XRGB_1555, 195 MDP_RGBX_5551, 196 MDP_XRGB_4444, 197 MDP_RGBX_4444, 198 MDP_ABGR_1555, 199 MDP_BGRA_5551, 200 MDP_XBGR_1555, 201 MDP_BGRX_5551, 202 MDP_ABGR_4444, 203 MDP_BGRA_4444, 204 MDP_XBGR_4444, 205 MDP_BGRX_4444, 206 MDP_ABGR_8888, 207 MDP_XBGR_8888, 208 MDP_RGBA_1010102, 209 MDP_ARGB_2101010, 210 MDP_RGBX_1010102, 211 MDP_XRGB_2101010, 212 MDP_BGRA_1010102, 213 MDP_ABGR_2101010, 214 MDP_BGRX_1010102, 215 MDP_XBGR_2101010, 216 MDP_RGBA_1010102_UBWC, 217 MDP_RGBX_1010102_UBWC, 218 MDP_Y_CBCR_H2V2_P010, 219 MDP_Y_CBCR_H2V2_TP10_UBWC, 220 MDP_CRYCBY_H2V1, /* CrYCbY interleave */ 221 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 222 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 223 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 224 }; 225 226 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 227 228 enum { 229 PMEM_IMG, 230 FB_IMG, 231 }; 232 233 enum { 234 HSIC_HUE = 0, 235 HSIC_SAT, 236 HSIC_INT, 237 HSIC_CON, 238 NUM_HSIC_PARAM, 239 }; 240 241 enum mdss_mdp_max_bw_mode { 242 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 243 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 244 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 245 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 246 }; 247 248 #define MDSS_MDP_ROT_ONLY 0x80 249 #define MDSS_MDP_RIGHT_MIXER 0x100 250 #define MDSS_MDP_DUAL_PIPE 0x200 251 252 /* mdp_blit_req flag values */ 253 #define MDP_ROT_NOP 0 254 #define MDP_FLIP_LR 0x1 255 #define MDP_FLIP_UD 0x2 256 #define MDP_ROT_90 0x4 257 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 258 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 259 #define MDP_DITHER 0x8 260 #define MDP_BLUR 0x10 261 #define MDP_BLEND_FG_PREMULT 0x20000 262 #define MDP_IS_FG 0x40000 263 #define MDP_SOLID_FILL 0x00000020 264 #define MDP_VPU_PIPE 0x00000040 265 #define MDP_DEINTERLACE 0x80000000 266 #define MDP_SHARPENING 0x40000000 267 #define MDP_NO_DMA_BARRIER_START 0x20000000 268 #define MDP_NO_DMA_BARRIER_END 0x10000000 269 #define MDP_NO_BLIT 0x08000000 270 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 271 #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 272 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 273 #define MDP_BLIT_SRC_GEM 0x04000000 274 #define MDP_BLIT_DST_GEM 0x02000000 275 #define MDP_BLIT_NON_CACHED 0x01000000 276 #define MDP_OV_PIPE_SHARE 0x00800000 277 #define MDP_DEINTERLACE_ODD 0x00400000 278 #define MDP_OV_PLAY_NOWAIT 0x00200000 279 #define MDP_SOURCE_ROTATED_90 0x00100000 280 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 281 #define MDP_BACKEND_COMPOSITION 0x00040000 282 #define MDP_BORDERFILL_SUPPORTED 0x00010000 283 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 284 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 285 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 286 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 287 #define MDP_BWC_EN 0x00000400 288 #define MDP_DECIMATION_EN 0x00000800 289 #define MDP_SMP_FORCE_ALLOC 0x00200000 290 #define MDP_TRANSP_NOP 0xffffffff 291 #define MDP_ALPHA_NOP 0xff 292 293 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 294 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 295 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 296 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 297 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 298 /* Sentinel: Don't use! */ 299 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 300 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 301 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 302 303 #define MDP_DEEP_COLOR_YUV444 0x1 304 #define MDP_DEEP_COLOR_RGB30B 0x2 305 #define MDP_DEEP_COLOR_RGB36B 0x4 306 #define MDP_DEEP_COLOR_RGB48B 0x8 307 308 struct mdp_rect { 309 uint32_t x; 310 uint32_t y; 311 uint32_t w; 312 uint32_t h; 313 }; 314 315 struct mdp_img { 316 uint32_t width; 317 uint32_t height; 318 uint32_t format; 319 uint32_t offset; 320 int memory_id; /* the file descriptor */ 321 uint32_t priv; 322 }; 323 324 struct mult_factor { 325 uint32_t numer; 326 uint32_t denom; 327 }; 328 329 /* 330 * {3x3} + {3} ccs matrix 331 */ 332 333 #define MDP_CCS_RGB2YUV 0 334 #define MDP_CCS_YUV2RGB 1 335 336 #define MDP_CCS_SIZE 9 337 #define MDP_BV_SIZE 3 338 339 struct mdp_ccs { 340 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 341 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 342 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 343 }; 344 345 struct mdp_csc { 346 int id; 347 uint32_t csc_mv[9]; 348 uint32_t csc_pre_bv[3]; 349 uint32_t csc_post_bv[3]; 350 uint32_t csc_pre_lv[6]; 351 uint32_t csc_post_lv[6]; 352 }; 353 354 /* The version of the mdp_blit_req structure so that 355 * user applications can selectively decide which functionality 356 * to include 357 */ 358 359 #define MDP_BLIT_REQ_VERSION 3 360 361 struct color { 362 uint32_t r; 363 uint32_t g; 364 uint32_t b; 365 uint32_t alpha; 366 }; 367 368 struct mdp_blit_req { 369 struct mdp_img src; 370 struct mdp_img dst; 371 struct mdp_rect src_rect; 372 struct mdp_rect dst_rect; 373 struct color const_color; 374 uint32_t alpha; 375 uint32_t transp_mask; 376 uint32_t flags; 377 int sharpening_strength; /* -127 <--> 127, default 64 */ 378 uint8_t color_space; 379 uint32_t fps; 380 }; 381 382 struct mdp_blit_req_list { 383 uint32_t count; 384 struct mdp_blit_req req[]; 385 }; 386 387 #define MSMFB_DATA_VERSION 2 388 389 struct msmfb_data { 390 uint32_t offset; 391 int memory_id; 392 int id; 393 uint32_t flags; 394 uint32_t priv; 395 uint32_t iova; 396 }; 397 398 #define MSMFB_NEW_REQUEST -1 399 400 struct msmfb_overlay_data { 401 uint32_t id; 402 struct msmfb_data data; 403 uint32_t version_key; 404 struct msmfb_data plane1_data; 405 struct msmfb_data plane2_data; 406 struct msmfb_data dst_data; 407 }; 408 409 struct msmfb_img { 410 uint32_t width; 411 uint32_t height; 412 uint32_t format; 413 }; 414 415 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 416 struct msmfb_writeback_data { 417 struct msmfb_data buf_info; 418 struct msmfb_img img; 419 }; 420 421 #define MDP_PP_OPS_ENABLE 0x1 422 #define MDP_PP_OPS_READ 0x2 423 #define MDP_PP_OPS_WRITE 0x4 424 #define MDP_PP_OPS_DISABLE 0x8 425 #define MDP_PP_IGC_FLAG_ROM0 0x10 426 #define MDP_PP_IGC_FLAG_ROM1 0x20 427 428 429 #define MDSS_PP_DSPP_CFG 0x000 430 #define MDSS_PP_SSPP_CFG 0x100 431 #define MDSS_PP_LM_CFG 0x200 432 #define MDSS_PP_WB_CFG 0x300 433 434 #define MDSS_PP_ARG_MASK 0x3C00 435 #define MDSS_PP_ARG_NUM 4 436 #define MDSS_PP_ARG_SHIFT 10 437 #define MDSS_PP_LOCATION_MASK 0x0300 438 #define MDSS_PP_LOGICAL_MASK 0x00FF 439 440 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 441 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 442 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 443 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 444 445 446 struct mdp_qseed_cfg { 447 uint32_t table_num; 448 uint32_t ops; 449 uint32_t len; 450 uint32_t *data; 451 }; 452 453 struct mdp_sharp_cfg { 454 uint32_t flags; 455 uint32_t strength; 456 uint32_t edge_thr; 457 uint32_t smooth_thr; 458 uint32_t noise_thr; 459 }; 460 461 struct mdp_qseed_cfg_data { 462 uint32_t block; 463 struct mdp_qseed_cfg qseed_data; 464 }; 465 466 #define MDP_OVERLAY_PP_CSC_CFG 0x1 467 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 468 #define MDP_OVERLAY_PP_PA_CFG 0x4 469 #define MDP_OVERLAY_PP_IGC_CFG 0x8 470 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 471 #define MDP_OVERLAY_PP_HIST_CFG 0x20 472 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 473 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 474 #define MDP_OVERLAY_PP_PCC_CFG 0x100 475 476 #define MDP_CSC_FLAG_ENABLE 0x1 477 #define MDP_CSC_FLAG_YUV_IN 0x2 478 #define MDP_CSC_FLAG_YUV_OUT 0x4 479 480 #define MDP_CSC_MATRIX_COEFF_SIZE 9 481 #define MDP_CSC_CLAMP_SIZE 6 482 #define MDP_CSC_BIAS_SIZE 3 483 484 struct mdp_csc_cfg { 485 /* flags for enable CSC, toggling RGB,YUV input/output */ 486 uint32_t flags; 487 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 488 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 489 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 490 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 491 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 492 }; 493 494 struct mdp_csc_cfg_data { 495 uint32_t block; 496 struct mdp_csc_cfg csc_data; 497 }; 498 499 struct mdp_pa_cfg { 500 uint32_t flags; 501 uint32_t hue_adj; 502 uint32_t sat_adj; 503 uint32_t val_adj; 504 uint32_t cont_adj; 505 }; 506 507 struct mdp_pa_mem_col_cfg { 508 uint32_t color_adjust_p0; 509 uint32_t color_adjust_p1; 510 uint32_t hue_region; 511 uint32_t sat_region; 512 uint32_t val_region; 513 }; 514 515 #define MDP_SIX_ZONE_LUT_SIZE 384 516 517 /* PA Write/Read extension flags */ 518 #define MDP_PP_PA_HUE_ENABLE 0x10 519 #define MDP_PP_PA_SAT_ENABLE 0x20 520 #define MDP_PP_PA_VAL_ENABLE 0x40 521 #define MDP_PP_PA_CONT_ENABLE 0x80 522 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 523 #define MDP_PP_PA_SKIN_ENABLE 0x200 524 #define MDP_PP_PA_SKY_ENABLE 0x400 525 #define MDP_PP_PA_FOL_ENABLE 0x800 526 527 /* PA masks */ 528 /* Masks used in PA v1_7 only */ 529 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 530 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 531 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 532 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 533 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 534 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 535 /* Masks used in all PAv2 versions */ 536 #define MDP_PP_PA_HUE_MASK 0x1000 537 #define MDP_PP_PA_SAT_MASK 0x2000 538 #define MDP_PP_PA_VAL_MASK 0x4000 539 #define MDP_PP_PA_CONT_MASK 0x8000 540 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 541 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 542 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 543 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 544 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 545 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 546 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 547 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 548 549 /* Flags for setting PA saturation and value hold */ 550 #define MDP_PP_PA_LEFT_HOLD 0x1 551 #define MDP_PP_PA_RIGHT_HOLD 0x2 552 553 struct mdp_pa_v2_data { 554 /* Mask bits for PA features */ 555 uint32_t flags; 556 uint32_t global_hue_adj; 557 uint32_t global_sat_adj; 558 uint32_t global_val_adj; 559 uint32_t global_cont_adj; 560 struct mdp_pa_mem_col_cfg skin_cfg; 561 struct mdp_pa_mem_col_cfg sky_cfg; 562 struct mdp_pa_mem_col_cfg fol_cfg; 563 uint32_t six_zone_len; 564 uint32_t six_zone_thresh; 565 uint32_t *six_zone_curve_p0; 566 uint32_t *six_zone_curve_p1; 567 }; 568 569 struct mdp_pa_mem_col_data_v1_7 { 570 uint32_t color_adjust_p0; 571 uint32_t color_adjust_p1; 572 uint32_t color_adjust_p2; 573 uint32_t blend_gain; 574 uint8_t sat_hold; 575 uint8_t val_hold; 576 uint32_t hue_region; 577 uint32_t sat_region; 578 uint32_t val_region; 579 }; 580 581 struct mdp_pa_data_v1_7 { 582 uint32_t mode; 583 uint32_t global_hue_adj; 584 uint32_t global_sat_adj; 585 uint32_t global_val_adj; 586 uint32_t global_cont_adj; 587 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 588 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 589 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 590 uint32_t six_zone_thresh; 591 uint32_t six_zone_adj_p0; 592 uint32_t six_zone_adj_p1; 593 uint8_t six_zone_sat_hold; 594 uint8_t six_zone_val_hold; 595 uint32_t six_zone_len; 596 uint32_t *six_zone_curve_p0; 597 uint32_t *six_zone_curve_p1; 598 }; 599 600 601 struct mdp_pa_v2_cfg_data { 602 uint32_t version; 603 uint32_t block; 604 uint32_t flags; 605 struct mdp_pa_v2_data pa_v2_data; 606 void *cfg_payload; 607 }; 608 609 610 enum { 611 mdp_igc_rec601 = 1, 612 mdp_igc_rec709, 613 mdp_igc_srgb, 614 mdp_igc_custom, 615 mdp_igc_rec_max, 616 }; 617 618 struct mdp_igc_lut_data { 619 uint32_t block; 620 uint32_t version; 621 uint32_t len, ops; 622 uint32_t *c0_c1_data; 623 uint32_t *c2_data; 624 void *cfg_payload; 625 }; 626 627 struct mdp_igc_lut_data_v1_7 { 628 uint32_t table_fmt; 629 uint32_t len; 630 uint32_t *c0_c1_data; 631 uint32_t *c2_data; 632 }; 633 634 struct mdp_igc_lut_data_payload { 635 uint32_t table_fmt; 636 uint32_t len; 637 uint64_t c0_c1_data; 638 uint64_t c2_data; 639 uint32_t strength; 640 }; 641 642 struct mdp_histogram_cfg { 643 uint32_t ops; 644 uint32_t block; 645 uint8_t frame_cnt; 646 uint8_t bit_mask; 647 uint16_t num_bins; 648 }; 649 650 struct mdp_hist_lut_data_v1_7 { 651 uint32_t len; 652 uint32_t *data; 653 }; 654 655 struct mdp_hist_lut_data { 656 uint32_t block; 657 uint32_t version; 658 uint32_t hist_lut_first; 659 uint32_t ops; 660 uint32_t len; 661 uint32_t *data; 662 void *cfg_payload; 663 }; 664 665 struct mdp_pcc_coeff { 666 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 667 }; 668 669 struct mdp_pcc_coeff_v1_7 { 670 uint32_t c, r, g, b, rg, gb, rb, rgb; 671 }; 672 673 struct mdp_pcc_data_v1_7 { 674 struct mdp_pcc_coeff_v1_7 r, g, b; 675 }; 676 677 struct mdp_pcc_cfg_data { 678 uint32_t version; 679 uint32_t block; 680 uint32_t ops; 681 struct mdp_pcc_coeff r, g, b; 682 void *cfg_payload; 683 }; 684 685 enum { 686 mdp_lut_igc, 687 mdp_lut_pgc, 688 mdp_lut_hist, 689 mdp_lut_rgb, 690 mdp_lut_max, 691 }; 692 struct mdp_overlay_pp_params { 693 uint32_t config_ops; 694 struct mdp_csc_cfg csc_cfg; 695 struct mdp_qseed_cfg qseed_cfg[2]; 696 struct mdp_pa_cfg pa_cfg; 697 struct mdp_pa_v2_data pa_v2_cfg; 698 struct mdp_igc_lut_data igc_cfg; 699 struct mdp_sharp_cfg sharp_cfg; 700 struct mdp_histogram_cfg hist_cfg; 701 struct mdp_hist_lut_data hist_lut_cfg; 702 /* PAv2 cfg data for PA 2.x versions */ 703 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 704 struct mdp_pcc_cfg_data pcc_cfg_data; 705 }; 706 707 /** 708 * enum mdss_mdp_blend_op - Different blend operations set by userspace 709 * 710 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 711 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 712 * would appear opaque in case fg plane alpha is 713 * 0xff. 714 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 715 * alpha pre-multiplication done. If fg plane alpha 716 * is less than 0xff, apply modulation as well. This 717 * operation is intended on layers having alpha 718 * channel. 719 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 720 * pre-multiplied. Apply pre-multiplication. If fg 721 * plane alpha is less than 0xff, apply modulation as 722 * well. 723 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 724 * mdp. 725 */ 726 enum mdss_mdp_blend_op { 727 BLEND_OP_NOT_DEFINED = 0, 728 BLEND_OP_OPAQUE, 729 BLEND_OP_PREMULTIPLIED, 730 BLEND_OP_COVERAGE, 731 BLEND_OP_MAX, 732 }; 733 734 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 735 #define MAX_PLANES 4 736 struct mdp_scale_data { 737 uint8_t enable_pxl_ext; 738 739 int init_phase_x[MAX_PLANES]; 740 int phase_step_x[MAX_PLANES]; 741 int init_phase_y[MAX_PLANES]; 742 int phase_step_y[MAX_PLANES]; 743 744 int num_ext_pxls_left[MAX_PLANES]; 745 int num_ext_pxls_right[MAX_PLANES]; 746 int num_ext_pxls_top[MAX_PLANES]; 747 int num_ext_pxls_btm[MAX_PLANES]; 748 749 int left_ftch[MAX_PLANES]; 750 int left_rpt[MAX_PLANES]; 751 int right_ftch[MAX_PLANES]; 752 int right_rpt[MAX_PLANES]; 753 754 int top_rpt[MAX_PLANES]; 755 int btm_rpt[MAX_PLANES]; 756 int top_ftch[MAX_PLANES]; 757 int btm_ftch[MAX_PLANES]; 758 759 uint32_t roi_w[MAX_PLANES]; 760 }; 761 762 /** 763 * enum mdp_overlay_pipe_type - Different pipe type set by userspace 764 * 765 * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. 766 * @PIPE_TYPE_VIG: VIG pipe. 767 * @PIPE_TYPE_RGB: RGB pipe. 768 * @PIPE_TYPE_DMA: DMA pipe. 769 * @PIPE_TYPE_CURSOR: CURSOR pipe. 770 * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. 771 */ 772 enum mdp_overlay_pipe_type { 773 PIPE_TYPE_AUTO = 0, 774 PIPE_TYPE_VIG, 775 PIPE_TYPE_RGB, 776 PIPE_TYPE_DMA, 777 PIPE_TYPE_CURSOR, 778 PIPE_TYPE_MAX, 779 }; 780 781 /** 782 * struct mdp_overlay - overlay surface structure 783 * @src: Source image information (width, height, format). 784 * @src_rect: Source crop rectangle, portion of image that will be fetched. 785 * This should always be within boundaries of source image. 786 * @dst_rect: Destination rectangle, the position and size of image on screen. 787 * This should always be within panel boundaries. 788 * @z_order: Blending stage to occupy in display, if multiple layers are 789 * present, highest z_order usually means the top most visible 790 * layer. The range acceptable is from 0-3 to support blending 791 * up to 4 layers. 792 * @is_fg: This flag is used to disable blending of any layers with z_order 793 * less than this overlay. It means that any layers with z_order 794 * less than this layer will not be blended and will be replaced 795 * by the background border color. 796 * @alpha: Used to set plane opacity. The range can be from 0-255, where 797 * 0 means completely transparent and 255 means fully opaque. 798 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 799 * image matching this color will be transparent when blending. 800 * The color should be in same format as the source image format. 801 * @flags: This is used to customize operation of overlay. See MDP flags 802 * for more information. 803 * @pipe_type: Used to specify the type of overlay pipe. 804 * @user_data: DEPRECATED* Used to store user application specific information. 805 * @bg_color: Solid color used to fill the overlay surface when no source 806 * buffer is provided. 807 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 808 * dropped for each pixel that is fetched from a line. The value 809 * given should be power of two of decimation amount. 810 * 0: no decimation 811 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 812 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 813 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 814 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 815 * @vert_deci: Vertical decimation value, this indicates the amount of lines 816 * dropped for each line that is fetched from overlay. The value 817 * given should be power of two of decimation amount. 818 * 0: no decimation 819 * 1: decimation by 2 (drop 1 line for each line fetched) 820 * 2: decimation by 4 (drop 3 lines for each line fetched) 821 * 3: decimation by 8 (drop 7 lines for each line fetched) 822 * 4: decimation by 16 (drop 15 lines for each line fetched) 823 * @overlay_pp_cfg: Overlay post processing configuration, for more information 824 * see struct mdp_overlay_pp_params. 825 * @priority: Priority is returned by the driver when overlay is set for the 826 * first time. It indicates the priority of the underlying pipe 827 * serving the overlay. This priority can be used by user-space 828 * in source split when pipes are re-used and shuffled around to 829 * reduce fallbacks. 830 */ 831 struct mdp_overlay { 832 struct msmfb_img src; 833 struct mdp_rect src_rect; 834 struct mdp_rect dst_rect; 835 uint32_t z_order; /* stage number */ 836 uint32_t is_fg; /* control alpha & transp */ 837 uint32_t alpha; 838 uint32_t blend_op; 839 uint32_t transp_mask; 840 uint32_t flags; 841 uint32_t pipe_type; 842 uint32_t id; 843 uint8_t priority; 844 uint32_t user_data[6]; 845 uint32_t bg_color; 846 uint8_t horz_deci; 847 uint8_t vert_deci; 848 struct mdp_overlay_pp_params overlay_pp_cfg; 849 struct mdp_scale_data scale; 850 uint8_t color_space; 851 uint32_t frame_rate; 852 }; 853 854 struct msmfb_overlay_3d { 855 uint32_t is_3d; 856 uint32_t width; 857 uint32_t height; 858 }; 859 860 861 struct msmfb_overlay_blt { 862 uint32_t enable; 863 uint32_t offset; 864 uint32_t width; 865 uint32_t height; 866 uint32_t bpp; 867 }; 868 869 struct mdp_histogram { 870 uint32_t frame_cnt; 871 uint32_t bin_cnt; 872 uint32_t *r; 873 uint32_t *g; 874 uint32_t *b; 875 }; 876 877 #define MISR_CRC_BATCH_SIZE 32 878 enum { 879 DISPLAY_MISR_EDP, 880 DISPLAY_MISR_DSI0, 881 DISPLAY_MISR_DSI1, 882 DISPLAY_MISR_HDMI, 883 DISPLAY_MISR_LCDC, 884 DISPLAY_MISR_MDP, 885 DISPLAY_MISR_ATV, 886 DISPLAY_MISR_DSI_CMD, 887 DISPLAY_MISR_MAX 888 }; 889 890 enum { 891 MISR_OP_NONE, 892 MISR_OP_SFM, 893 MISR_OP_MFM, 894 MISR_OP_BM, 895 MISR_OP_MAX 896 }; 897 898 struct mdp_misr { 899 uint32_t block_id; 900 uint32_t frame_count; 901 uint32_t crc_op_mode; 902 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 903 }; 904 905 /* 906 * mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 907 * 908 * MDP_BLOCK_RESERVED is provided for backward compatibility and is 909 * deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 910 * instead. 911 * 912 * MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 913 * same for others. 914 */ 915 916 enum { 917 MDP_BLOCK_RESERVED = 0, 918 MDP_BLOCK_OVERLAY_0, 919 MDP_BLOCK_OVERLAY_1, 920 MDP_BLOCK_VG_1, 921 MDP_BLOCK_VG_2, 922 MDP_BLOCK_RGB_1, 923 MDP_BLOCK_RGB_2, 924 MDP_BLOCK_DMA_P, 925 MDP_BLOCK_DMA_S, 926 MDP_BLOCK_DMA_E, 927 MDP_BLOCK_OVERLAY_2, 928 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 929 MDP_LOGICAL_BLOCK_DISP_1, 930 MDP_LOGICAL_BLOCK_DISP_2, 931 MDP_BLOCK_MAX, 932 }; 933 934 /* 935 * mdp_histogram_start_req is used to provide the parameters for 936 * histogram start request 937 */ 938 939 struct mdp_histogram_start_req { 940 uint32_t block; 941 uint8_t frame_cnt; 942 uint8_t bit_mask; 943 uint16_t num_bins; 944 }; 945 946 /* 947 * mdp_histogram_data is used to return the histogram data, once 948 * the histogram is done/stopped/cance 949 */ 950 951 struct mdp_histogram_data { 952 uint32_t block; 953 uint32_t bin_cnt; 954 uint32_t *c0; 955 uint32_t *c1; 956 uint32_t *c2; 957 uint32_t *extra_info; 958 }; 959 960 961 #define GC_LUT_ENTRIES_V1_7 512 962 963 struct mdp_ar_gc_lut_data { 964 uint32_t x_start; 965 uint32_t slope; 966 uint32_t offset; 967 }; 968 969 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 970 struct mdp_pgc_lut_data { 971 uint32_t version; 972 uint32_t block; 973 uint32_t flags; 974 uint8_t num_r_stages; 975 uint8_t num_g_stages; 976 uint8_t num_b_stages; 977 struct mdp_ar_gc_lut_data *r_data; 978 struct mdp_ar_gc_lut_data *g_data; 979 struct mdp_ar_gc_lut_data *b_data; 980 void *cfg_payload; 981 }; 982 983 #define PGC_LUT_ENTRIES 1024 984 struct mdp_pgc_lut_data_v1_7 { 985 uint32_t len; 986 uint32_t *c0_data; 987 uint32_t *c1_data; 988 uint32_t *c2_data; 989 }; 990 991 /* 992 * mdp_rgb_lut_data is used to provide parameters for configuring the 993 * generic RGB lut in case of gamma correction or other LUT updation usecases 994 */ 995 struct mdp_rgb_lut_data { 996 uint32_t flags; 997 uint32_t lut_type; 998 struct fb_cmap cmap; 999 }; 1000 1001 enum { 1002 mdp_rgb_lut_gc, 1003 mdp_rgb_lut_hist, 1004 }; 1005 1006 struct mdp_lut_cfg_data { 1007 uint32_t lut_type; 1008 union { 1009 struct mdp_igc_lut_data igc_lut_data; 1010 struct mdp_pgc_lut_data pgc_lut_data; 1011 struct mdp_hist_lut_data hist_lut_data; 1012 struct mdp_rgb_lut_data rgb_lut_data; 1013 } data; 1014 }; 1015 1016 struct mdp_bl_scale_data { 1017 uint32_t min_lvl; 1018 uint32_t scale; 1019 }; 1020 1021 struct mdp_pa_cfg_data { 1022 uint32_t block; 1023 struct mdp_pa_cfg pa_data; 1024 }; 1025 1026 #define MDP_DITHER_DATA_V1_7_SZ 16 1027 1028 struct mdp_dither_data_v1_7 { 1029 uint32_t g_y_depth; 1030 uint32_t r_cr_depth; 1031 uint32_t b_cb_depth; 1032 uint32_t len; 1033 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 1034 uint32_t temporal_en; 1035 }; 1036 1037 struct mdp_pa_dither_data { 1038 uint64_t data_flags; 1039 uint32_t matrix_sz; 1040 uint64_t matrix_data; 1041 uint32_t strength; 1042 uint32_t offset_en; 1043 }; 1044 1045 struct mdp_dither_cfg_data { 1046 uint32_t version; 1047 uint32_t block; 1048 uint32_t flags; 1049 uint32_t mode; 1050 uint32_t g_y_depth; 1051 uint32_t r_cr_depth; 1052 uint32_t b_cb_depth; 1053 void *cfg_payload; 1054 }; 1055 1056 #define MDP_GAMUT_TABLE_NUM 8 1057 #define MDP_GAMUT_TABLE_NUM_V1_7 4 1058 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 1059 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 1060 #define MDP_GAMUT_SCALE_OFF_SZ 16 1061 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 1062 1063 struct mdp_gamut_cfg_data { 1064 uint32_t block; 1065 uint32_t flags; 1066 uint32_t version; 1067 /* v1 version specific params */ 1068 uint32_t gamut_first; 1069 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 1070 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 1071 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 1072 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 1073 /* params for newer versions of gamut */ 1074 void *cfg_payload; 1075 }; 1076 1077 enum { 1078 mdp_gamut_fine_mode = 0x1, 1079 mdp_gamut_coarse_mode, 1080 }; 1081 1082 struct mdp_gamut_data_v1_7 { 1083 uint32_t mode; 1084 uint32_t map_en; 1085 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 1086 uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1087 uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1088 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1089 uint32_t *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1090 }; 1091 1092 struct mdp_calib_config_data { 1093 uint32_t ops; 1094 uint32_t addr; 1095 uint32_t data; 1096 }; 1097 1098 struct mdp_calib_config_buffer { 1099 uint32_t ops; 1100 uint32_t size; 1101 uint32_t *buffer; 1102 }; 1103 1104 struct mdp_calib_dcm_state { 1105 uint32_t ops; 1106 uint32_t dcm_state; 1107 }; 1108 1109 enum { 1110 DCM_UNINIT, 1111 DCM_UNBLANK, 1112 DCM_ENTER, 1113 DCM_EXIT, 1114 DCM_BLANK, 1115 DTM_ENTER, 1116 DTM_EXIT, 1117 }; 1118 1119 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 1120 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 1121 #define MDSS_PP_SPLIT_MASK 0x30000000 1122 1123 #define MDSS_MAX_BL_BRIGHTNESS 255 1124 #define AD_BL_LIN_LEN 256 1125 #define AD_BL_ATT_LUT_LEN 33 1126 1127 #define MDSS_AD_MODE_AUTO_BL 0x0 1128 #define MDSS_AD_MODE_AUTO_STR 0x1 1129 #define MDSS_AD_MODE_TARG_STR 0x3 1130 #define MDSS_AD_MODE_MAN_STR 0x7 1131 #define MDSS_AD_MODE_CALIB 0xF 1132 1133 #define MDP_PP_AD_INIT 0x10 1134 #define MDP_PP_AD_CFG 0x20 1135 1136 struct mdss_ad_init { 1137 uint32_t asym_lut[33]; 1138 uint32_t color_corr_lut[33]; 1139 uint8_t i_control[2]; 1140 uint16_t black_lvl; 1141 uint16_t white_lvl; 1142 uint8_t var; 1143 uint8_t limit_ampl; 1144 uint8_t i_dither; 1145 uint8_t slope_max; 1146 uint8_t slope_min; 1147 uint8_t dither_ctl; 1148 uint8_t format; 1149 uint8_t auto_size; 1150 uint16_t frame_w; 1151 uint16_t frame_h; 1152 uint8_t logo_v; 1153 uint8_t logo_h; 1154 uint32_t alpha; 1155 uint32_t alpha_base; 1156 uint32_t al_thresh; 1157 uint32_t bl_lin_len; 1158 uint32_t bl_att_len; 1159 uint32_t *bl_lin; 1160 uint32_t *bl_lin_inv; 1161 uint32_t *bl_att_lut; 1162 }; 1163 1164 #define MDSS_AD_BL_CTRL_MODE_EN 1 1165 #define MDSS_AD_BL_CTRL_MODE_DIS 0 1166 struct mdss_ad_cfg { 1167 uint32_t mode; 1168 uint32_t al_calib_lut[33]; 1169 uint16_t backlight_min; 1170 uint16_t backlight_max; 1171 uint16_t backlight_scale; 1172 uint16_t amb_light_min; 1173 uint16_t filter[2]; 1174 uint16_t calib[4]; 1175 uint8_t strength_limit; 1176 uint8_t t_filter_recursion; 1177 uint16_t stab_itr; 1178 uint32_t bl_ctrl_mode; 1179 }; 1180 1181 struct mdss_ad_bl_cfg { 1182 uint32_t bl_min_delta; 1183 uint32_t bl_low_limit; 1184 }; 1185 1186 /* ops uses standard MDP_PP_* flags */ 1187 struct mdss_ad_init_cfg { 1188 uint32_t ops; 1189 union { 1190 struct mdss_ad_init init; 1191 struct mdss_ad_cfg cfg; 1192 } params; 1193 }; 1194 1195 /* mode uses MDSS_AD_MODE_* flags */ 1196 struct mdss_ad_input { 1197 uint32_t mode; 1198 union { 1199 uint32_t amb_light; 1200 uint32_t strength; 1201 uint32_t calib_bl; 1202 } in; 1203 uint32_t output; 1204 }; 1205 1206 #define MDSS_CALIB_MODE_BL 0x1 1207 struct mdss_calib_cfg { 1208 uint32_t ops; 1209 uint32_t calib_mask; 1210 }; 1211 1212 enum { 1213 mdp_op_pcc_cfg, 1214 mdp_op_csc_cfg, 1215 mdp_op_lut_cfg, 1216 mdp_op_qseed_cfg, 1217 mdp_bl_scale_cfg, 1218 mdp_op_pa_cfg, 1219 mdp_op_pa_v2_cfg, 1220 mdp_op_dither_cfg, 1221 mdp_op_gamut_cfg, 1222 mdp_op_calib_cfg, 1223 mdp_op_ad_cfg, 1224 mdp_op_ad_input, 1225 mdp_op_calib_mode, 1226 mdp_op_calib_buffer, 1227 mdp_op_calib_dcm_state, 1228 mdp_op_max, 1229 mdp_op_pa_dither_cfg, 1230 mdp_op_ad_bl_cfg, 1231 mdp_op_pp_max = 255, 1232 }; 1233 #define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg 1234 #define mdp_op_pp_max mdp_op_pp_max 1235 1236 #define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg 1237 1238 enum { 1239 WB_FORMAT_NV12, 1240 WB_FORMAT_RGB_565, 1241 WB_FORMAT_RGB_888, 1242 WB_FORMAT_xRGB_8888, 1243 WB_FORMAT_ARGB_8888, 1244 WB_FORMAT_BGRA_8888, 1245 WB_FORMAT_BGRX_8888, 1246 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 1247 }; 1248 1249 struct msmfb_mdp_pp { 1250 uint32_t op; 1251 union { 1252 struct mdp_pcc_cfg_data pcc_cfg_data; 1253 struct mdp_csc_cfg_data csc_cfg_data; 1254 struct mdp_lut_cfg_data lut_cfg_data; 1255 struct mdp_qseed_cfg_data qseed_cfg_data; 1256 struct mdp_bl_scale_data bl_scale_data; 1257 struct mdp_pa_cfg_data pa_cfg_data; 1258 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1259 struct mdp_dither_cfg_data dither_cfg_data; 1260 struct mdp_gamut_cfg_data gamut_cfg_data; 1261 struct mdp_calib_config_data calib_cfg; 1262 struct mdss_ad_init_cfg ad_init_cfg; 1263 struct mdss_calib_cfg mdss_calib_cfg; 1264 struct mdss_ad_input ad_input; 1265 struct mdp_calib_config_buffer calib_buffer; 1266 struct mdp_calib_dcm_state calib_dcm; 1267 struct mdss_ad_bl_cfg ad_bl_cfg; 1268 } data; 1269 }; 1270 1271 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1272 enum { 1273 metadata_op_none, 1274 metadata_op_base_blend, 1275 metadata_op_frame_rate, 1276 metadata_op_vic, 1277 metadata_op_wb_format, 1278 metadata_op_wb_secure, 1279 metadata_op_get_caps, 1280 metadata_op_crc, 1281 metadata_op_get_ion_fd, 1282 metadata_op_max 1283 }; 1284 1285 struct mdp_blend_cfg { 1286 uint32_t is_premultiplied; 1287 }; 1288 1289 struct mdp_mixer_cfg { 1290 uint32_t writeback_format; 1291 uint32_t alpha; 1292 }; 1293 1294 struct mdss_hw_caps { 1295 uint32_t mdp_rev; 1296 uint8_t rgb_pipes; 1297 uint8_t vig_pipes; 1298 uint8_t dma_pipes; 1299 uint8_t max_smp_cnt; 1300 uint8_t smp_per_pipe; 1301 uint32_t features; 1302 }; 1303 1304 struct msmfb_metadata { 1305 uint32_t op; 1306 uint32_t flags; 1307 union { 1308 struct mdp_misr misr_request; 1309 struct mdp_blend_cfg blend_cfg; 1310 struct mdp_mixer_cfg mixer_cfg; 1311 uint32_t panel_frame_rate; 1312 uint32_t video_info_code; 1313 struct mdss_hw_caps caps; 1314 uint8_t secure_en; 1315 int fbmem_ionfd; 1316 } data; 1317 }; 1318 1319 #define MDP_MAX_FENCE_FD 32 1320 #define MDP_BUF_SYNC_FLAG_WAIT 1 1321 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1322 1323 struct mdp_buf_sync { 1324 uint32_t flags; 1325 uint32_t acq_fen_fd_cnt; 1326 uint32_t session_id; 1327 int *acq_fen_fd; 1328 int *rel_fen_fd; 1329 int *retire_fen_fd; 1330 }; 1331 1332 struct mdp_async_blit_req_list { 1333 struct mdp_buf_sync sync; 1334 uint32_t count; 1335 struct mdp_blit_req req[]; 1336 }; 1337 1338 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1339 1340 struct mdp_display_commit { 1341 uint32_t flags; 1342 uint32_t wait_for_finish; 1343 struct fb_var_screeninfo var; 1344 /* 1345 * user needs to follow guidelines as per below rules 1346 * 1. source split is enabled: l_roi = roi and r_roi = 0 1347 * 2. source split is disabled: 1348 * 2.1 split display: l_roi = l_roi and r_roi = r_roi 1349 * 2.2 non split display: l_roi = roi and r_roi = 0 1350 */ 1351 struct mdp_rect l_roi; 1352 struct mdp_rect r_roi; 1353 }; 1354 1355 /** 1356 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1357 * @num_overlays: Number of overlay layers as part of the frame. 1358 * @overlay_list: Pointer to a list of overlay structures identifying 1359 * the layers as part of the frame 1360 * @flags: Flags can be used to extend behavior. 1361 * @processed_overlays: Output parameter indicating how many pipes were 1362 * successful. If there are no errors this number should 1363 * match num_overlays. Otherwise it will indicate the last 1364 * successful index for overlay that couldn't be set. 1365 */ 1366 struct mdp_overlay_list { 1367 uint32_t num_overlays; 1368 struct mdp_overlay **overlay_list; 1369 uint32_t flags; 1370 uint32_t processed_overlays; 1371 }; 1372 1373 struct mdp_page_protection { 1374 uint32_t page_protection; 1375 }; 1376 1377 1378 struct mdp_mixer_info { 1379 int pndx; 1380 int pnum; 1381 int ptype; 1382 int mixer_num; 1383 int z_order; 1384 }; 1385 1386 #define MAX_PIPE_PER_MIXER 7 1387 1388 struct msmfb_mixer_info_req { 1389 int mixer_num; 1390 int cnt; 1391 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1392 }; 1393 1394 enum { 1395 DISPLAY_SUBSYSTEM_ID, 1396 ROTATOR_SUBSYSTEM_ID, 1397 }; 1398 1399 enum { 1400 MDP_IOMMU_DOMAIN_CP, 1401 MDP_IOMMU_DOMAIN_NS, 1402 }; 1403 1404 enum { 1405 MDP_WRITEBACK_MIRROR_OFF, 1406 MDP_WRITEBACK_MIRROR_ON, 1407 MDP_WRITEBACK_MIRROR_PAUSE, 1408 MDP_WRITEBACK_MIRROR_RESUME, 1409 }; 1410 1411 enum mdp_color_space { 1412 MDP_CSC_ITU_R_601, 1413 MDP_CSC_ITU_R_601_FR, 1414 MDP_CSC_ITU_R_709, 1415 }; 1416 1417 /* 1418 * These definitions are a continuation of the mdp_color_space enum above 1419 */ 1420 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1421 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1422 enum { 1423 mdp_igc_v1_7 = 1, 1424 mdp_igc_vmax, 1425 mdp_hist_lut_v1_7, 1426 mdp_hist_lut_vmax, 1427 mdp_pgc_v1_7, 1428 mdp_pgc_vmax, 1429 mdp_dither_v1_7, 1430 mdp_dither_vmax, 1431 mdp_gamut_v1_7, 1432 mdp_gamut_vmax, 1433 mdp_pa_v1_7, 1434 mdp_pa_vmax, 1435 mdp_pcc_v1_7, 1436 mdp_pcc_vmax, 1437 mdp_pp_legacy, 1438 mdp_dither_pa_v1_7, 1439 mdp_igc_v3, 1440 mdp_pp_unknown = 255 1441 }; 1442 1443 #define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 1444 #define mdp_pp_unknown mdp_pp_unknown 1445 #define mdp_igc_v3 mdp_igc_v3 1446 1447 /* PP Features */ 1448 enum { 1449 IGC = 1, 1450 PCC, 1451 GC, 1452 PA, 1453 GAMUT, 1454 DITHER, 1455 QSEED, 1456 HIST_LUT, 1457 HIST, 1458 PP_FEATURE_MAX, 1459 PA_DITHER, 1460 PP_MAX_FEATURES = 25, 1461 }; 1462 1463 #define PA_DITHER PA_DITHER 1464 #define PP_MAX_FEATURES PP_MAX_FEATURES 1465 1466 struct mdp_pp_feature_version { 1467 uint32_t pp_feature; 1468 uint32_t version_info; 1469 }; 1470 #endif /* _MSM_MDP_H_*/ 1471