1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ 2 /* 3 * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _MSM_MDP_EXT_H_ 7 #define _MSM_MDP_EXT_H_ 8 9 #include <linux/msm_mdp.h> 10 11 #define MDP_IOCTL_MAGIC 'S' 12 /* atomic commit ioctl used for validate and commit request */ 13 #define MSMFB_ATOMIC_COMMIT _IOWR(MDP_IOCTL_MAGIC, 128, void *) 14 15 /* 16 * Ioctl for updating the layer position asynchronously. Initially, pipes 17 * should be configured with MDP_LAYER_ASYNC flag set during the atomic commit, 18 * after which any number of position update calls can be made. This would 19 * enable multiple position updates within a single vsync. However, the screen 20 * update would happen only after vsync, which would pick the latest update. 21 * 22 * Limitations: 23 * - Currently supported only for video mode panels with single LM or dual LM 24 * with source_split enabled. 25 * - Only position update is supported with no scaling/cropping. 26 * - Async layers should have unique z_order. 27 */ 28 #define MSMFB_ASYNC_POSITION_UPDATE _IOWR(MDP_IOCTL_MAGIC, 129, \ 29 struct mdp_position_update) 30 31 /* 32 * Ioctl for sending the config information. 33 * QSEED3 coefficeint LUT tables is passed by the user space using this IOCTL. 34 */ 35 #define MSMFB_MDP_SET_CFG _IOW(MDP_IOCTL_MAGIC, 130, \ 36 struct mdp_set_cfg) 37 38 /* 39 * Ioctl for setting the PLL PPM. 40 * PLL PPM is passed by the user space using this IOCTL. 41 */ 42 #define MSMFB_MDP_SET_PANEL_PPM _IOW(MDP_IOCTL_MAGIC, 131, int) 43 44 /* 45 * To allow proper structure padding for 64bit/32bit target 46 */ 47 #ifdef __LP64 48 #define MDP_LAYER_COMMIT_V1_PAD 2 49 #else 50 #define MDP_LAYER_COMMIT_V1_PAD 3 51 #endif 52 53 /********************************************************************** 54 * LAYER FLAG CONFIGURATION 55 **********************************************************************/ 56 /* left-right layer flip flag */ 57 #define MDP_LAYER_FLIP_LR 0x1 58 59 /* up-down layer flip flag */ 60 #define MDP_LAYER_FLIP_UD 0x2 61 62 /* 63 * This flag enables pixel extension for the current layer. Validate/commit 64 * call uses scale parameters when this flag is enabled. 65 */ 66 #define MDP_LAYER_ENABLE_PIXEL_EXT 0x4 67 68 /* Flag indicates that layer is foreground layer */ 69 #define MDP_LAYER_FORGROUND 0x8 70 71 /* Flag indicates that layer is associated with secure session */ 72 #define MDP_LAYER_SECURE_SESSION 0x10 73 74 /* 75 * Flag indicates that layer is drawing solid fill. Validate/commit call 76 * does not expect buffer when this flag is enabled. 77 */ 78 #define MDP_LAYER_SOLID_FILL 0x20 79 80 /* Layer format is deinterlace */ 81 #define MDP_LAYER_DEINTERLACE 0x40 82 83 /* layer contains bandwidth compressed format data */ 84 #define MDP_LAYER_BWC 0x80 85 86 /* layer is async position updatable */ 87 #define MDP_LAYER_ASYNC 0x100 88 89 /* layer contains postprocessing configuration data */ 90 #define MDP_LAYER_PP 0x200 91 92 /* Flag indicates that layer is associated with secure display session */ 93 #define MDP_LAYER_SECURE_DISPLAY_SESSION 0x400 94 95 /* Flag enabled qseed3 scaling for the current layer */ 96 #define MDP_LAYER_ENABLE_QSEED3_SCALE 0x800 97 98 /* 99 * layer will work in multirect mode, where single hardware should 100 * fetch multiple rectangles with a single hardware 101 */ 102 #define MDP_LAYER_MULTIRECT_ENABLE 0x1000 103 104 /* 105 * if flag present and multirect is enabled, multirect will work in parallel 106 * fetch mode, otherwise it will default to serial fetch mode. 107 */ 108 #define MDP_LAYER_MULTIRECT_PARALLEL_MODE 0x2000 109 110 111 /* Flag indicates that layer is associated with secure camera session */ 112 #define MDP_LAYER_SECURE_CAMERA_SESSION 0x4000 113 114 /********************************************************************** 115 * DESTINATION SCALER FLAG CONFIGURATION 116 **********************************************************************/ 117 118 /* Enable/disable Destination scaler */ 119 #define MDP_DESTSCALER_ENABLE 0x1 120 121 /* 122 * Indicating mdp_destination_scaler_data contains 123 * Scaling parameter update. Can be set anytime. 124 */ 125 #define MDP_DESTSCALER_SCALE_UPDATE 0x2 126 127 /* 128 * Indicating mdp_destination_scaler_data contains 129 * Detail enhancement setting update. Can be set anytime. 130 */ 131 #define MDP_DESTSCALER_ENHANCER_UPDATE 0x4 132 133 /* 134 * Indicating a partial update to panel ROI. ROI can be 135 * applied anytime when Destination scaler is enabled. 136 */ 137 #define MDP_DESTSCALER_ROI_ENABLE 0x8 138 139 /********************************************************************** 140 * VALIDATE/COMMIT FLAG CONFIGURATION 141 **********************************************************************/ 142 143 /* 144 * Client enables it to inform that call is to validate layers before commit. 145 * If this flag is not set then driver will use MSMFB_ATOMIC_COMMIT for commit. 146 */ 147 #define MDP_VALIDATE_LAYER 0x01 148 149 /* 150 * This flag is only valid for commit call. Commit behavior is synchronous 151 * when this flag is defined. It blocks current call till processing is 152 * complete. Behavior is asynchronous otherwise. 153 */ 154 #define MDP_COMMIT_WAIT_FOR_FINISH 0x02 155 156 /* 157 * This flag is only valid for commit call and used for debugging purpose. It 158 * forces the to wait for sync fences. 159 */ 160 #define MDP_COMMIT_SYNC_FENCE_WAIT 0x04 161 162 /* Flag to enable AVR(Adaptive variable refresh) feature. */ 163 #define MDP_COMMIT_AVR_EN 0x08 164 165 /* 166 * Flag to select one shot mode when AVR feature is enabled. 167 * Default mode is continuous mode. 168 */ 169 #define MDP_COMMIT_AVR_ONE_SHOT_MODE 0x10 170 171 /* Flag to indicate dual partial ROI update */ 172 #define MDP_COMMIT_PARTIAL_UPDATE_DUAL_ROI 0x20 173 174 /* Flag to update brightness when commit */ 175 #define MDP_COMMIT_UPDATE_BRIGHTNESS 0x40 176 177 /* Flag to enable concurrent writeback for the frame */ 178 #define MDP_COMMIT_CWB_EN 0x800 179 180 /* 181 * Flag to select DSPP as the data point for CWB. If CWB 182 * is enabled without this flag, LM will be selected as data point. 183 */ 184 #define MDP_COMMIT_CWB_DSPP 0x1000 185 186 /* 187 * Flag to indicate that rectangle number is being assigned 188 * by userspace in multi-rectangle mode 189 */ 190 #define MDP_COMMIT_RECT_NUM 0x2000 191 192 #define MDP_COMMIT_VERSION_1_0 0x00010000 193 194 #define OUT_LAYER_COLOR_SPACE 195 196 /* From CEA.861.3 */ 197 #define MDP_HDR_EOTF_SMTPE_ST2084 0x2 198 #define MDP_HDR_EOTF_HLG 0x3 199 200 /* From Vesa DPv1.4 - Pixel Encoding - Table 2-120 */ 201 #define MDP_PIXEL_ENCODING_RGB 0x0 202 #define MDP_PIXEL_ENCODING_YCBCR_444 0x1 203 #define MDP_PIXEL_ENCODING_YCBCR_422 0x2 204 #define MDP_PIXEL_ENCODING_YCBCR_420 0x3 205 #define MDP_PIXEL_ENCODING_Y_ONLY 0x4 206 #define MDP_PIXEL_ENCODING_RAW 0x5 207 208 /* From Vesa DPv1.4 - Colorimetry Formats - Table 2-120 */ 209 /* RGB - used with MDP_DP_PIXEL_ENCODING_RGB */ 210 #define MDP_COLORIMETRY_RGB_SRGB 0x0 211 #define MDP_COLORIMETRY_RGB_WIDE_FIXED_POINT 0x1 212 #define MDP_COLORIMETRY_RGB_WIDE_FLOAT_POINT 0x2 213 #define MDP_COLORIMETRY_RGB_ADOBE 0x3 214 #define MDP_COLORIMETRY_RGB_DPI_P3 0x4 215 #define MDP_COLORIMETRY_RGB_CUSTOM 0x5 216 #define MDP_COLORIMETRY_RGB_ITU_R_BT_2020 0x6 217 218 /* YUV - used with MDP_DP_PIXEL_ENCODING_YCBCR(444 or 422 or 420) */ 219 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_601 0x0 220 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_709 0x1 221 #define MDP_COLORIMETRY_YCBCR_XV_YCC_601 0x2 222 #define MDP_COLORIMETRY_YCBCR_XV_YCC_709 0x3 223 #define MDP_COLORIMETRY_YCBCR_S_YCC_601 0x4 224 #define MDP_COLORIMETRY_YCBCR_ADOBE_YCC_601 0x5 225 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_2020_YCBCR_CONST 0x6 226 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_2020_YCBCR 0x7 227 228 /* Dynamic Range - Table 2-120 */ 229 /* Full range */ 230 #define MDP_DYNAMIC_RANGE_VESA 0x0 231 /* Limited range */ 232 #define MDP_DYNAMIC_RANGE_CEA 0x1 233 234 /* Bits per component(bpc) for Pixel encoding format RGB from Table 2-120 */ 235 #define MDP_RGB_6_BPC 0x0 236 #define MDP_RGB_8_BPC 0x1 237 #define MDP_RGB_10_BPC 0x2 238 #define MDP_RGB_12_BPC 0x3 239 #define MDP_RGB_16_BPC 0x4 240 241 /* 242 * Bits per component(bpc) for Pixel encoding format YCbCr444, YCbCr422, 243 * YCbCr420 and Y only 244 * from Table 2-120 245 */ 246 #define MDP_YUV_8_BPC 0x1 247 #define MDP_YUV_10_BPC 0x2 248 #define MDP_YUV_12_BPC 0x3 249 #define MDP_YUV_16_BPC 0x4 250 251 /* Bits per component(bpc) for Pixel encoding format RAW from Table 2-120 */ 252 #define MDP_RAW_6_BPC 0x1 253 #define MDP_RAW_7_BPC 0x2 254 #define MDP_RAW_8_BPC 0x3 255 #define MDP_RAW_10_BPC 0x4 256 #define MDP_RAW_12_BPC 0x5 257 #define MDP_RAW_14_BPC 0x6 258 #define MDP_RAW16_BPC 0x7 259 260 /* Content Type - Table 2-120 */ 261 #define MDP_CONTENT_TYPE_NOT_DEFINED 0x0 262 #define MDP_CONTENT_TYPE_GRAPHICS 0x1 263 #define MDP_CONTENT_TYPE_PHOTO 0x2 264 #define MDP_CONTENT_TYPE_VIDEO 0x3 265 #define MDP_CONTENT_TYPE_GAME 0x4 266 267 /********************************************************************** 268 * Configuration structures 269 * All parameters are input to driver unless mentioned output parameter 270 * explicitly. 271 **********************************************************************/ 272 struct mdp_layer_plane { 273 /* DMA buffer file descriptor information. */ 274 int fd; 275 276 /* Pixel offset in the dma buffer. */ 277 uint32_t offset; 278 279 /* Number of bytes in one scan line including padding bytes. */ 280 uint32_t stride; 281 }; 282 283 struct mdp_layer_buffer { 284 /* layer width in pixels. */ 285 uint32_t width; 286 287 /* layer height in pixels. */ 288 uint32_t height; 289 290 /* 291 * layer format in DRM-style fourcc, refer drm_fourcc.h for 292 * standard formats 293 */ 294 uint32_t format; 295 296 /* plane to hold the fd, offset, etc for all color components */ 297 struct mdp_layer_plane planes[MAX_PLANES]; 298 299 /* valid planes count in layer planes list */ 300 uint32_t plane_count; 301 302 /* compression ratio factor, value depends on the pixel format */ 303 struct mult_factor comp_ratio; 304 305 /* 306 * SyncFence associated with this buffer. It is used in two ways. 307 * 308 * 1. Driver waits to consume the buffer till producer signals in case 309 * of primary and external display. 310 * 311 * 2. Writeback device uses buffer structure for output buffer where 312 * driver is producer. However, client sends the fence with buffer to 313 * indicate that consumer is still using the buffer and it is not ready 314 * for new content. 315 */ 316 int fence; 317 318 /* 32bits reserved value for future usage. */ 319 uint32_t reserved; 320 }; 321 322 /* 323 * One layer holds configuration for one pipe. If client wants to stage single 324 * layer on two pipes then it should send two different layers with relative 325 * (x,y) information. Client must send same information during validate and 326 * commit call. Commit call may fail if client sends different layer information 327 * attached to same pipe during validate and commit. Device invalidate the pipe 328 * once it receives the vsync for that commit. 329 */ 330 struct mdp_input_layer { 331 /* 332 * Flag to enable/disable properties for layer configuration. Refer 333 * layer flag configuration section for all possible flags. 334 */ 335 uint32_t flags; 336 337 /* 338 * Pipe selection for this layer by client. Client provides the index 339 * in validate and commit call. Device reserves the pipe once validate 340 * is successful. Device only uses validated pipe during commit call. 341 * If client sends different layer/pipe configuration in validate & 342 * commit then commit may fail. 343 */ 344 uint32_t pipe_ndx; 345 346 /* 347 * Horizontal decimation value, this indicates the amount of pixels 348 * dropped for each pixel that is fetched from a line. It does not 349 * result in bandwidth reduction because pixels are still fetched from 350 * memory but dropped internally by hardware. 351 * The decimation value given should be power of two of decimation 352 * amount. 353 * 0: no decimation 354 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 355 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 356 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 357 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 358 */ 359 uint8_t horz_deci; 360 361 /* 362 * Vertical decimation value, this indicates the amount of lines 363 * dropped for each line that is fetched from overlay. It saves 364 * bandwidth because decimated pixels are not fetched. 365 * The decimation value given should be power of two of decimation 366 * amount. 367 * 0: no decimation 368 * 1: decimation by 2 (drop 1 line for each line fetched) 369 * 2: decimation by 4 (drop 3 lines for each line fetched) 370 * 3: decimation by 8 (drop 7 lines for each line fetched) 371 * 4: decimation by 16 (drop 15 lines for each line fetched) 372 */ 373 uint8_t vert_deci; 374 375 /* 376 * Used to set plane opacity. The range can be from 0-255, where 377 * 0 means completely transparent and 255 means fully opaque. 378 */ 379 uint8_t alpha; 380 381 /* 382 * Blending stage to occupy in display, if multiple layers are present, 383 * highest z_order usually means the top most visible layer. The range 384 * acceptable is from 0-7 to support blending up to 8 layers. 385 */ 386 uint16_t z_order; 387 388 /* 389 * Color used as color key for transparency. Any pixel in fetched 390 * image matching this color will be transparent when blending. 391 * The color should be in same format as the source image format. 392 */ 393 uint32_t transp_mask; 394 395 /* 396 * Solid color used to fill the overlay surface when no source 397 * buffer is provided. 398 */ 399 uint32_t bg_color; 400 401 /* blend operation defined in "mdss_mdp_blend_op" enum. */ 402 enum mdss_mdp_blend_op blend_op; 403 404 /* color space of the source */ 405 enum mdp_color_space color_space; 406 407 /* 408 * Source crop rectangle, portion of image that will be fetched. This 409 * should always be within boundaries of source image. 410 */ 411 struct mdp_rect src_rect; 412 413 /* 414 * Destination rectangle, the position and size of image on screen. 415 * This should always be within panel boundaries. 416 */ 417 struct mdp_rect dst_rect; 418 419 /* Scaling parameters. */ 420 void *scale; 421 422 /* Buffer attached with each layer. Device uses it for commit call. */ 423 struct mdp_layer_buffer buffer; 424 425 /* 426 * Source side post processing configuration information for each 427 * layer. 428 */ 429 void *pp_info; 430 431 /* 432 * This is an output parameter. 433 * 434 * Only for validate call. Frame buffer device sets error code 435 * based on validate call failure scenario. 436 */ 437 int error_code; 438 439 /* 440 * For source pipes supporting multi-rectangle, this field identifies 441 * the rectangle index of the source pipe. 442 */ 443 uint32_t rect_num; 444 445 /* 32bits reserved value for future usage. */ 446 uint32_t reserved[5]; 447 }; 448 449 struct mdp_output_layer { 450 /* 451 * Flag to enable/disable properties for layer configuration. Refer 452 * layer flag config section for all possible flags. 453 */ 454 uint32_t flags; 455 456 /* 457 * Writeback destination selection for output. Client provides the index 458 * in validate and commit call. 459 */ 460 uint32_t writeback_ndx; 461 462 /* Buffer attached with output layer. Device uses it for commit call */ 463 struct mdp_layer_buffer buffer; 464 465 /* color space of the destination */ 466 enum mdp_color_space color_space; 467 468 /* 32bits reserved value for future usage. */ 469 uint32_t reserved[5]; 470 }; 471 472 /* 473 * Destination scaling info structure holds setup parameters for upscaling 474 * setting in the destination scaling block. 475 */ 476 struct mdp_destination_scaler_data { 477 /* 478 * Flag to switch between mode for destination scaler. Please Refer to 479 * destination scaler flag config for all possible setting. 480 */ 481 uint32_t flags; 482 483 /* 484 * Destination scaler selection index. Client provides the index in 485 * validate and commit call. 486 */ 487 uint32_t dest_scaler_ndx; 488 489 /* 490 * LM width configuration per Destination scaling updates 491 */ 492 uint32_t lm_width; 493 494 /* 495 * LM height configuration per Destination scaling updates 496 */ 497 uint32_t lm_height; 498 499 /* 500 * The scaling parameters for all the mode except disable. For 501 * disabling the scaler, there is no need to provide the scale. 502 * A userspace pointer points to struct mdp_scale_data_v2. 503 */ 504 uint64_t scale; 505 506 /* 507 * Panel ROI is used when partial update is required in 508 * current commit call. 509 */ 510 struct mdp_rect panel_roi; 511 }; 512 513 /* 514 * Commit structure holds layer stack send by client for validate and commit 515 * call. If layers are different between validate and commit call then commit 516 * call will also do validation. In such case, commit may fail. 517 */ 518 struct mdp_layer_commit_v1 { 519 /* 520 * Flag to enable/disable properties for commit/validate call. Refer 521 * validate/commit flag config section for all possible flags. 522 */ 523 uint32_t flags; 524 525 /* 526 * This is an output parameter. 527 * 528 * Frame buffer device provides release fence handle to client. It 529 * triggers release fence when display hardware has consumed all the 530 * buffers attached to this commit call and buffer is ready for reuse 531 * for primary and external. For writeback case, it triggers it when 532 * output buffer is ready for consumer. 533 */ 534 int release_fence; 535 536 /* 537 * Left_roi is optional configuration. Client configures it only when 538 * partial update is enabled. It defines the "region of interest" on 539 * left part of panel when it is split display. For non-split display, 540 * it defines the "region of interest" on the panel. 541 */ 542 struct mdp_rect left_roi; 543 544 /* 545 * Right_roi is optional configuration. Client configures it only when 546 * partial update is enabled. It defines the "region of interest" on 547 * right part of panel for split display configuration. It is not 548 * required for non-split display. 549 */ 550 struct mdp_rect right_roi; 551 552 /* Pointer to a list of input layers for composition. */ 553 struct mdp_input_layer *input_layers; 554 555 /* Input layer count present in input list */ 556 uint32_t input_layer_cnt; 557 558 /* 559 * Output layer for writeback display. It supports only one 560 * layer as output layer. This is not required for primary 561 * and external displays 562 */ 563 struct mdp_output_layer *output_layer; 564 565 /* 566 * This is an output parameter. 567 * 568 * Frame buffer device provides retire fence handle if 569 * COMMIT_RETIRE_FENCE flag is set in commit call. It triggers 570 * retire fence when current layers are swapped with new layers 571 * on display hardware. For video mode panel and writeback, 572 * retire fence and release fences are triggered at the same 573 * time while command mode panel triggers release fence first 574 * (on pingpong done) and retire fence (on rdptr done) 575 * after that. 576 */ 577 int retire_fence; 578 579 /* 580 * Scaler data and control for setting up destination scaler. 581 * A userspace pointer that points to a list of 582 * struct mdp_destination_scaler_data. 583 */ 584 void *dest_scaler; 585 586 /* 587 * Represents number of Destination scaler data provied by userspace. 588 */ 589 uint32_t dest_scaler_cnt; 590 591 /* Backlight level that would update when display commit */ 592 uint32_t bl_level; 593 594 /* 32-bits reserved value for future usage. */ 595 uint32_t reserved[MDP_LAYER_COMMIT_V1_PAD]; 596 }; 597 598 /* 599 * mdp_overlay_list - argument for ioctl MSMFB_ATOMIC_COMMIT 600 */ 601 struct mdp_layer_commit { 602 /* 603 * 32bit version indicates the commit structure selection 604 * from union. Lower 16bits indicates the minor version while 605 * higher 16bits indicates the major version. It selects the 606 * commit structure based on major version selection. Minor version 607 * indicates that reserved fields are in use. 608 * 609 * Current supported version is 1.0 (Major:1 Minor:0) 610 */ 611 uint32_t version; 612 union { 613 /* Layer commit/validate definition for V1 */ 614 struct mdp_layer_commit_v1 commit_v1; 615 }; 616 }; 617 618 struct mdp_point { 619 uint32_t x; 620 uint32_t y; 621 }; 622 623 /* 624 * Async updatable layers. One layer holds configuration for one pipe. 625 */ 626 struct mdp_async_layer { 627 /* 628 * Flag to enable/disable properties for layer configuration. Refer 629 * layer flag config section for all possible flags. 630 */ 631 uint32_t flags; 632 633 /* 634 * Pipe selection for this layer by client. Client provides the 635 * pipe index that the device reserved during ATOMIC_COMMIT. 636 */ 637 uint32_t pipe_ndx; 638 639 /* Source start x,y. */ 640 struct mdp_point src; 641 642 /* Destination start x,y. */ 643 struct mdp_point dst; 644 645 /* 646 * This is an output parameter. 647 * 648 * Frame buffer device sets error code based on the failure. 649 */ 650 int error_code; 651 652 uint32_t reserved[3]; 653 }; 654 655 /* 656 * mdp_position_update - argument for ioctl MSMFB_ASYNC_POSITION_UPDATE 657 */ 658 struct mdp_position_update { 659 /* Pointer to a list of async updatable input layers */ 660 struct mdp_async_layer *input_layers; 661 662 /* Input layer count present in input list */ 663 uint32_t input_layer_cnt; 664 }; 665 666 #define MAX_DET_CURVES 3 667 struct mdp_det_enhance_data { 668 uint32_t enable; 669 int16_t sharpen_level1; 670 int16_t sharpen_level2; 671 uint16_t clip; 672 uint16_t limit; 673 uint16_t thr_quiet; 674 uint16_t thr_dieout; 675 uint16_t thr_low; 676 uint16_t thr_high; 677 uint16_t prec_shift; 678 int16_t adjust_a[MAX_DET_CURVES]; 679 int16_t adjust_b[MAX_DET_CURVES]; 680 int16_t adjust_c[MAX_DET_CURVES]; 681 }; 682 683 /* Flags to enable Scaler and its sub components */ 684 #define ENABLE_SCALE 0x1 685 #define ENABLE_DETAIL_ENHANCE 0x2 686 #define ENABLE_DIRECTION_DETECTION 0x4 687 688 /* LUT configuration flags */ 689 #define SCALER_LUT_SWAP 0x1 690 #define SCALER_LUT_DIR_WR 0x2 691 #define SCALER_LUT_Y_CIR_WR 0x4 692 #define SCALER_LUT_UV_CIR_WR 0x8 693 #define SCALER_LUT_Y_SEP_WR 0x10 694 #define SCALER_LUT_UV_SEP_WR 0x20 695 696 /* Y/RGB and UV filter configuration */ 697 #define FILTER_EDGE_DIRECTED_2D 0x0 698 #define FILTER_CIRCULAR_2D 0x1 699 #define FILTER_SEPARABLE_1D 0x2 700 #define FILTER_BILINEAR 0x3 701 702 /* Alpha filters */ 703 #define FILTER_ALPHA_DROP_REPEAT 0x0 704 #define FILTER_ALPHA_BILINEAR 0x1 705 706 /** 707 * struct mdp_scale_data_v2 708 * Driver uses this new Data structure for storing all scaling params 709 * This structure contains all pixel extension data and QSEED3 filter 710 * configuration and coefficient table indices 711 */ 712 struct mdp_scale_data_v2 { 713 uint32_t enable; 714 715 /* Init phase values */ 716 int32_t init_phase_x[MAX_PLANES]; 717 int32_t phase_step_x[MAX_PLANES]; 718 int32_t init_phase_y[MAX_PLANES]; 719 int32_t phase_step_y[MAX_PLANES]; 720 721 /* This should be set to toal horizontal pixels 722 * left + right + width 723 */ 724 uint32_t num_ext_pxls_left[MAX_PLANES]; 725 726 /* Unused param for backward compatibility */ 727 uint32_t num_ext_pxls_right[MAX_PLANES]; 728 729 /* This should be set to vertical pixels 730 * top + bottom + height 731 */ 732 uint32_t num_ext_pxls_top[MAX_PLANES]; 733 734 /* Unused param for backward compatibility */ 735 uint32_t num_ext_pxls_btm[MAX_PLANES]; 736 737 /* over fetch pixels */ 738 int32_t left_ftch[MAX_PLANES]; 739 int32_t left_rpt[MAX_PLANES]; 740 int32_t right_ftch[MAX_PLANES]; 741 int32_t right_rpt[MAX_PLANES]; 742 743 /* Repeat pixels */ 744 uint32_t top_rpt[MAX_PLANES]; 745 uint32_t btm_rpt[MAX_PLANES]; 746 uint32_t top_ftch[MAX_PLANES]; 747 uint32_t btm_ftch[MAX_PLANES]; 748 749 uint32_t roi_w[MAX_PLANES]; 750 751 /* alpha plane can only be scaled using bilinear or pixel 752 * repeat/drop, specify these for Y and UV planes only 753 */ 754 uint32_t preload_x[MAX_PLANES]; 755 uint32_t preload_y[MAX_PLANES]; 756 uint32_t src_width[MAX_PLANES]; 757 uint32_t src_height[MAX_PLANES]; 758 759 uint32_t dst_width; 760 uint32_t dst_height; 761 762 uint32_t y_rgb_filter_cfg; 763 uint32_t uv_filter_cfg; 764 uint32_t alpha_filter_cfg; 765 uint32_t blend_cfg; 766 767 uint32_t lut_flag; 768 uint32_t dir_lut_idx; 769 770 /* for Y(RGB) and UV planes*/ 771 uint32_t y_rgb_cir_lut_idx; 772 uint32_t uv_cir_lut_idx; 773 uint32_t y_rgb_sep_lut_idx; 774 uint32_t uv_sep_lut_idx; 775 776 struct mdp_det_enhance_data detail_enhance; 777 778 /* reserved value for future usage. */ 779 uint64_t reserved[8]; 780 }; 781 782 /** 783 * struct mdp_scale_luts_info 784 * This struct pointer is received as payload in SET_CFG_IOCTL when the flags 785 * is set to MDP_QSEED3_LUT_CFG 786 * @dir_lut: Direction detection coefficients table 787 * @cir_lut: Circular coefficeints table 788 * @sep_lut: Separable coefficeints table 789 * @dir_lut_size: Size of direction coefficients table 790 * @cir_lut_size: Size of circular coefficients table 791 * @sep_lut_size: Size of separable coefficients table 792 */ 793 struct mdp_scale_luts_info { 794 uint64_t dir_lut; 795 uint64_t cir_lut; 796 uint64_t sep_lut; 797 uint32_t dir_lut_size; 798 uint32_t cir_lut_size; 799 uint32_t sep_lut_size; 800 }; 801 802 #define MDP_QSEED3_LUT_CFG 0x1 803 804 struct mdp_set_cfg { 805 uint64_t flags; 806 uint32_t len; 807 uint64_t payload; 808 }; 809 810 #define HDR_PRIMARIES_COUNT 3 811 812 #define MDP_HDR_STREAM 813 814 struct mdp_hdr_stream { 815 uint32_t eotf; 816 uint32_t display_primaries_x[HDR_PRIMARIES_COUNT]; 817 uint32_t display_primaries_y[HDR_PRIMARIES_COUNT]; 818 uint32_t white_point_x; 819 uint32_t white_point_y; 820 uint32_t max_luminance; 821 uint32_t min_luminance; 822 uint32_t max_content_light_level; 823 uint32_t max_average_light_level; 824 /* DP related */ 825 uint32_t pixel_encoding; 826 uint32_t colorimetry; 827 uint32_t range; 828 uint32_t bits_per_component; 829 uint32_t content_type; 830 uint32_t reserved[5]; 831 }; 832 833 /* hdr hdmi state takes possible values of 1, 2 and 4 respectively */ 834 #define HDR_ENABLE (1 << 0) 835 #define HDR_DISABLE (1 << 1) 836 #define HDR_RESET (1 << 2) 837 838 /* 839 * HDR Control 840 * This encapsulates the HDR metadata as well as a state control 841 * for the HDR metadata as required by the HDMI spec to send the 842 * relevant metadata depending on the state of the HDR playback. 843 * hdr_state: Controls HDR state, takes values HDR_ENABLE, HDR_DISABLE 844 * and HDR_RESET. 845 * hdr_meta: Metadata sent by the userspace for the HDR clip. 846 */ 847 848 struct mdp_hdr_stream_ctrl { 849 __u8 hdr_state; /* HDR state */ 850 struct mdp_hdr_stream hdr_stream; /* HDR metadata */ 851 }; 852 853 #endif 854