1 #ifndef _MSM_MDP_EXT_H_ 2 #define _MSM_MDP_EXT_H_ 3 4 #include <linux/msm_mdp.h> 5 6 #define MDP_IOCTL_MAGIC 'S' 7 /* atomic commit ioctl used for validate and commit request */ 8 #define MSMFB_ATOMIC_COMMIT _IOWR(MDP_IOCTL_MAGIC, 128, void *) 9 10 /* 11 * Ioctl for updating the layer position asynchronously. Initially, pipes 12 * should be configured with MDP_LAYER_ASYNC flag set during the atomic commit, 13 * after which any number of position update calls can be made. This would 14 * enable multiple position updates within a single vsync. However, the screen 15 * update would happen only after vsync, which would pick the latest update. 16 * 17 * Limitations: 18 * - Currently supported only for video mode panels with single LM or dual LM 19 * with source_split enabled. 20 * - Only position update is supported with no scaling/cropping. 21 * - Async layers should have unique z_order. 22 */ 23 #define MSMFB_ASYNC_POSITION_UPDATE _IOWR(MDP_IOCTL_MAGIC, 129, \ 24 struct mdp_position_update) 25 26 /* 27 * Ioctl for sending the config information. 28 * QSEED3 coefficeint LUT tables is passed by the user space using this IOCTL. 29 */ 30 #define MSMFB_MDP_SET_CFG _IOW(MDP_IOCTL_MAGIC, 130, \ 31 struct mdp_set_cfg) 32 33 /* 34 * Ioctl for setting the PLL PPM. 35 * PLL PPM is passed by the user space using this IOCTL. 36 */ 37 #define MSMFB_MDP_SET_PANEL_PPM _IOW(MDP_IOCTL_MAGIC, 131, int) 38 39 /* 40 * To allow proper structure padding for 64bit/32bit target 41 */ 42 #ifdef __LP64 43 #define MDP_LAYER_COMMIT_V1_PAD 2 44 #else 45 #define MDP_LAYER_COMMIT_V1_PAD 3 46 #endif 47 48 /********************************************************************** 49 * LAYER FLAG CONFIGURATION 50 **********************************************************************/ 51 /* left-right layer flip flag */ 52 #define MDP_LAYER_FLIP_LR 0x1 53 54 /* up-down layer flip flag */ 55 #define MDP_LAYER_FLIP_UD 0x2 56 57 /* 58 * This flag enables pixel extension for the current layer. Validate/commit 59 * call uses scale parameters when this flag is enabled. 60 */ 61 #define MDP_LAYER_ENABLE_PIXEL_EXT 0x4 62 63 /* Flag indicates that layer is foreground layer */ 64 #define MDP_LAYER_FORGROUND 0x8 65 66 /* Flag indicates that layer is associated with secure session */ 67 #define MDP_LAYER_SECURE_SESSION 0x10 68 69 /* 70 * Flag indicates that layer is drawing solid fill. Validate/commit call 71 * does not expect buffer when this flag is enabled. 72 */ 73 #define MDP_LAYER_SOLID_FILL 0x20 74 75 /* Layer format is deinterlace */ 76 #define MDP_LAYER_DEINTERLACE 0x40 77 78 /* layer contains bandwidth compressed format data */ 79 #define MDP_LAYER_BWC 0x80 80 81 /* layer is async position updatable */ 82 #define MDP_LAYER_ASYNC 0x100 83 84 /* layer contains postprocessing configuration data */ 85 #define MDP_LAYER_PP 0x200 86 87 /* Flag indicates that layer is associated with secure display session */ 88 #define MDP_LAYER_SECURE_DISPLAY_SESSION 0x400 89 90 /* Flag enabled qseed3 scaling for the current layer */ 91 #define MDP_LAYER_ENABLE_QSEED3_SCALE 0x800 92 93 /* 94 * layer will work in multirect mode, where single hardware should 95 * fetch multiple rectangles with a single hardware 96 */ 97 #define MDP_LAYER_MULTIRECT_ENABLE 0x1000 98 99 /* 100 * if flag present and multirect is enabled, multirect will work in parallel 101 * fetch mode, otherwise it will default to serial fetch mode. 102 */ 103 #define MDP_LAYER_MULTIRECT_PARALLEL_MODE 0x2000 104 105 106 /* Flag indicates that layer is associated with secure camera session */ 107 #define MDP_LAYER_SECURE_CAMERA_SESSION 0x4000 108 109 /********************************************************************** 110 * DESTINATION SCALER FLAG CONFIGURATION 111 **********************************************************************/ 112 113 /* Enable/disable Destination scaler */ 114 #define MDP_DESTSCALER_ENABLE 0x1 115 116 /* 117 * Indicating mdp_destination_scaler_data contains 118 * Scaling parameter update. Can be set anytime. 119 */ 120 #define MDP_DESTSCALER_SCALE_UPDATE 0x2 121 122 /* 123 * Indicating mdp_destination_scaler_data contains 124 * Detail enhancement setting update. Can be set anytime. 125 */ 126 #define MDP_DESTSCALER_ENHANCER_UPDATE 0x4 127 128 /* 129 * Indicating a partial update to panel ROI. ROI can be 130 * applied anytime when Destination scaler is enabled. 131 */ 132 #define MDP_DESTSCALER_ROI_ENABLE 0x8 133 134 /********************************************************************** 135 * VALIDATE/COMMIT FLAG CONFIGURATION 136 **********************************************************************/ 137 138 /* 139 * Client enables it to inform that call is to validate layers before commit. 140 * If this flag is not set then driver will use MSMFB_ATOMIC_COMMIT for commit. 141 */ 142 #define MDP_VALIDATE_LAYER 0x01 143 144 /* 145 * This flag is only valid for commit call. Commit behavior is synchronous 146 * when this flag is defined. It blocks current call till processing is 147 * complete. Behavior is asynchronous otherwise. 148 */ 149 #define MDP_COMMIT_WAIT_FOR_FINISH 0x02 150 151 /* 152 * This flag is only valid for commit call and used for debugging purpose. It 153 * forces the to wait for sync fences. 154 */ 155 #define MDP_COMMIT_SYNC_FENCE_WAIT 0x04 156 157 /* Flag to enable AVR(Adaptive variable refresh) feature. */ 158 #define MDP_COMMIT_AVR_EN 0x08 159 160 /* 161 * Flag to select one shot mode when AVR feature is enabled. 162 * Default mode is continuous mode. 163 */ 164 #define MDP_COMMIT_AVR_ONE_SHOT_MODE 0x10 165 166 /* Flag to indicate dual partial ROI update */ 167 #define MDP_COMMIT_PARTIAL_UPDATE_DUAL_ROI 0x20 168 169 /* Flag to update brightness when commit */ 170 #define MDP_COMMIT_UPDATE_BRIGHTNESS 0x40 171 172 /* Flag to enable concurrent writeback for the frame */ 173 #define MDP_COMMIT_CWB_EN 0x800 174 175 /* 176 * Flag to select DSPP as the data point for CWB. If CWB 177 * is enabled without this flag, LM will be selected as data point. 178 */ 179 #define MDP_COMMIT_CWB_DSPP 0x1000 180 181 /* 182 * Flag to indicate that rectangle number is being assigned 183 * by userspace in multi-rectangle mode 184 */ 185 #define MDP_COMMIT_RECT_NUM 0x2000 186 187 #define MDP_COMMIT_VERSION_1_0 0x00010000 188 189 #define OUT_LAYER_COLOR_SPACE 190 191 /* From CEA.861.3 */ 192 #define MDP_HDR_EOTF_SMTPE_ST2084 0x2 193 #define MDP_HDR_EOTF_HLG 0x3 194 195 /* From Vesa DPv1.4 - Pixel Encoding - Table 2-120 */ 196 #define MDP_PIXEL_ENCODING_RGB 0x0 197 #define MDP_PIXEL_ENCODING_YCBCR_444 0x1 198 #define MDP_PIXEL_ENCODING_YCBCR_422 0x2 199 #define MDP_PIXEL_ENCODING_YCBCR_420 0x3 200 #define MDP_PIXEL_ENCODING_Y_ONLY 0x4 201 #define MDP_PIXEL_ENCODING_RAW 0x5 202 203 /* From Vesa DPv1.4 - Colorimetry Formats - Table 2-120 */ 204 /* RGB - used with MDP_DP_PIXEL_ENCODING_RGB */ 205 #define MDP_COLORIMETRY_RGB_SRGB 0x0 206 #define MDP_COLORIMETRY_RGB_WIDE_FIXED_POINT 0x1 207 #define MDP_COLORIMETRY_RGB_WIDE_FLOAT_POINT 0x2 208 #define MDP_COLORIMETRY_RGB_ADOBE 0x3 209 #define MDP_COLORIMETRY_RGB_DPI_P3 0x4 210 #define MDP_COLORIMETRY_RGB_CUSTOM 0x5 211 #define MDP_COLORIMETRY_RGB_ITU_R_BT_2020 0x6 212 213 /* YUV - used with MDP_DP_PIXEL_ENCODING_YCBCR(444 or 422 or 420) */ 214 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_601 0x0 215 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_709 0x1 216 #define MDP_COLORIMETRY_YCBCR_XV_YCC_601 0x2 217 #define MDP_COLORIMETRY_YCBCR_XV_YCC_709 0x3 218 #define MDP_COLORIMETRY_YCBCR_S_YCC_601 0x4 219 #define MDP_COLORIMETRY_YCBCR_ADOBE_YCC_601 0x5 220 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_2020_YCBCR_CONST 0x6 221 #define MDP_COLORIMETRY_YCBCR_ITU_R_BT_2020_YCBCR 0x7 222 223 /* Dynamic Range - Table 2-120 */ 224 /* Full range */ 225 #define MDP_DYNAMIC_RANGE_VESA 0x0 226 /* Limited range */ 227 #define MDP_DYNAMIC_RANGE_CEA 0x1 228 229 /* Bits per component(bpc) for Pixel encoding format RGB from Table 2-120 */ 230 #define MDP_RGB_6_BPC 0x0 231 #define MDP_RGB_8_BPC 0x1 232 #define MDP_RGB_10_BPC 0x2 233 #define MDP_RGB_12_BPC 0x3 234 #define MDP_RGB_16_BPC 0x4 235 236 /* 237 * Bits per component(bpc) for Pixel encoding format YCbCr444, YCbCr422, 238 * YCbCr420 and Y only 239 * from Table 2-120 240 */ 241 #define MDP_YUV_8_BPC 0x1 242 #define MDP_YUV_10_BPC 0x2 243 #define MDP_YUV_12_BPC 0x3 244 #define MDP_YUV_16_BPC 0x4 245 246 /* Bits per component(bpc) for Pixel encoding format RAW from Table 2-120 */ 247 #define MDP_RAW_6_BPC 0x1 248 #define MDP_RAW_7_BPC 0x2 249 #define MDP_RAW_8_BPC 0x3 250 #define MDP_RAW_10_BPC 0x4 251 #define MDP_RAW_12_BPC 0x5 252 #define MDP_RAW_14_BPC 0x6 253 #define MDP_RAW16_BPC 0x7 254 255 /* Content Type - Table 2-120 */ 256 #define MDP_CONTENT_TYPE_NOT_DEFINED 0x0 257 #define MDP_CONTENT_TYPE_GRAPHICS 0x1 258 #define MDP_CONTENT_TYPE_PHOTO 0x2 259 #define MDP_CONTENT_TYPE_VIDEO 0x3 260 #define MDP_CONTENT_TYPE_GAME 0x4 261 262 /********************************************************************** 263 * Configuration structures 264 * All parameters are input to driver unless mentioned output parameter 265 * explicitly. 266 **********************************************************************/ 267 struct mdp_layer_plane { 268 /* DMA buffer file descriptor information. */ 269 int fd; 270 271 /* Pixel offset in the dma buffer. */ 272 uint32_t offset; 273 274 /* Number of bytes in one scan line including padding bytes. */ 275 uint32_t stride; 276 }; 277 278 struct mdp_layer_buffer { 279 /* layer width in pixels. */ 280 uint32_t width; 281 282 /* layer height in pixels. */ 283 uint32_t height; 284 285 /* 286 * layer format in DRM-style fourcc, refer drm_fourcc.h for 287 * standard formats 288 */ 289 uint32_t format; 290 291 /* plane to hold the fd, offset, etc for all color components */ 292 struct mdp_layer_plane planes[MAX_PLANES]; 293 294 /* valid planes count in layer planes list */ 295 uint32_t plane_count; 296 297 /* compression ratio factor, value depends on the pixel format */ 298 struct mult_factor comp_ratio; 299 300 /* 301 * SyncFence associated with this buffer. It is used in two ways. 302 * 303 * 1. Driver waits to consume the buffer till producer signals in case 304 * of primary and external display. 305 * 306 * 2. Writeback device uses buffer structure for output buffer where 307 * driver is producer. However, client sends the fence with buffer to 308 * indicate that consumer is still using the buffer and it is not ready 309 * for new content. 310 */ 311 int fence; 312 313 /* 32bits reserved value for future usage. */ 314 uint32_t reserved; 315 }; 316 317 /* 318 * One layer holds configuration for one pipe. If client wants to stage single 319 * layer on two pipes then it should send two different layers with relative 320 * (x,y) information. Client must send same information during validate and 321 * commit call. Commit call may fail if client sends different layer information 322 * attached to same pipe during validate and commit. Device invalidate the pipe 323 * once it receives the vsync for that commit. 324 */ 325 struct mdp_input_layer { 326 /* 327 * Flag to enable/disable properties for layer configuration. Refer 328 * layer flag configuration section for all possible flags. 329 */ 330 uint32_t flags; 331 332 /* 333 * Pipe selection for this layer by client. Client provides the index 334 * in validate and commit call. Device reserves the pipe once validate 335 * is successful. Device only uses validated pipe during commit call. 336 * If client sends different layer/pipe configuration in validate & 337 * commit then commit may fail. 338 */ 339 uint32_t pipe_ndx; 340 341 /* 342 * Horizontal decimation value, this indicates the amount of pixels 343 * dropped for each pixel that is fetched from a line. It does not 344 * result in bandwidth reduction because pixels are still fetched from 345 * memory but dropped internally by hardware. 346 * The decimation value given should be power of two of decimation 347 * amount. 348 * 0: no decimation 349 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 350 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 351 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 352 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 353 */ 354 uint8_t horz_deci; 355 356 /* 357 * Vertical decimation value, this indicates the amount of lines 358 * dropped for each line that is fetched from overlay. It saves 359 * bandwidth because decimated pixels are not fetched. 360 * The decimation value given should be power of two of decimation 361 * amount. 362 * 0: no decimation 363 * 1: decimation by 2 (drop 1 line for each line fetched) 364 * 2: decimation by 4 (drop 3 lines for each line fetched) 365 * 3: decimation by 8 (drop 7 lines for each line fetched) 366 * 4: decimation by 16 (drop 15 lines for each line fetched) 367 */ 368 uint8_t vert_deci; 369 370 /* 371 * Used to set plane opacity. The range can be from 0-255, where 372 * 0 means completely transparent and 255 means fully opaque. 373 */ 374 uint8_t alpha; 375 376 /* 377 * Blending stage to occupy in display, if multiple layers are present, 378 * highest z_order usually means the top most visible layer. The range 379 * acceptable is from 0-7 to support blending up to 8 layers. 380 */ 381 uint16_t z_order; 382 383 /* 384 * Color used as color key for transparency. Any pixel in fetched 385 * image matching this color will be transparent when blending. 386 * The color should be in same format as the source image format. 387 */ 388 uint32_t transp_mask; 389 390 /* 391 * Solid color used to fill the overlay surface when no source 392 * buffer is provided. 393 */ 394 uint32_t bg_color; 395 396 /* blend operation defined in "mdss_mdp_blend_op" enum. */ 397 enum mdss_mdp_blend_op blend_op; 398 399 /* color space of the source */ 400 enum mdp_color_space color_space; 401 402 /* 403 * Source crop rectangle, portion of image that will be fetched. This 404 * should always be within boundaries of source image. 405 */ 406 struct mdp_rect src_rect; 407 408 /* 409 * Destination rectangle, the position and size of image on screen. 410 * This should always be within panel boundaries. 411 */ 412 struct mdp_rect dst_rect; 413 414 /* Scaling parameters. */ 415 void *scale; 416 417 /* Buffer attached with each layer. Device uses it for commit call. */ 418 struct mdp_layer_buffer buffer; 419 420 /* 421 * Source side post processing configuration information for each 422 * layer. 423 */ 424 void *pp_info; 425 426 /* 427 * This is an output parameter. 428 * 429 * Only for validate call. Frame buffer device sets error code 430 * based on validate call failure scenario. 431 */ 432 int error_code; 433 434 /* 435 * For source pipes supporting multi-rectangle, this field identifies 436 * the rectangle index of the source pipe. 437 */ 438 uint32_t rect_num; 439 440 /* 32bits reserved value for future usage. */ 441 uint32_t reserved[5]; 442 }; 443 444 struct mdp_output_layer { 445 /* 446 * Flag to enable/disable properties for layer configuration. Refer 447 * layer flag config section for all possible flags. 448 */ 449 uint32_t flags; 450 451 /* 452 * Writeback destination selection for output. Client provides the index 453 * in validate and commit call. 454 */ 455 uint32_t writeback_ndx; 456 457 /* Buffer attached with output layer. Device uses it for commit call */ 458 struct mdp_layer_buffer buffer; 459 460 /* color space of the destination */ 461 enum mdp_color_space color_space; 462 463 /* 32bits reserved value for future usage. */ 464 uint32_t reserved[5]; 465 }; 466 467 /* 468 * Destination scaling info structure holds setup parameters for upscaling 469 * setting in the destination scaling block. 470 */ 471 struct mdp_destination_scaler_data { 472 /* 473 * Flag to switch between mode for destination scaler. Please Refer to 474 * destination scaler flag config for all possible setting. 475 */ 476 uint32_t flags; 477 478 /* 479 * Destination scaler selection index. Client provides the index in 480 * validate and commit call. 481 */ 482 uint32_t dest_scaler_ndx; 483 484 /* 485 * LM width configuration per Destination scaling updates 486 */ 487 uint32_t lm_width; 488 489 /* 490 * LM height configuration per Destination scaling updates 491 */ 492 uint32_t lm_height; 493 494 /* 495 * The scaling parameters for all the mode except disable. For 496 * disabling the scaler, there is no need to provide the scale. 497 * A userspace pointer points to struct mdp_scale_data_v2. 498 */ 499 uint64_t scale; 500 501 /* 502 * Panel ROI is used when partial update is required in 503 * current commit call. 504 */ 505 struct mdp_rect panel_roi; 506 }; 507 508 /* 509 * Commit structure holds layer stack send by client for validate and commit 510 * call. If layers are different between validate and commit call then commit 511 * call will also do validation. In such case, commit may fail. 512 */ 513 struct mdp_layer_commit_v1 { 514 /* 515 * Flag to enable/disable properties for commit/validate call. Refer 516 * validate/commit flag config section for all possible flags. 517 */ 518 uint32_t flags; 519 520 /* 521 * This is an output parameter. 522 * 523 * Frame buffer device provides release fence handle to client. It 524 * triggers release fence when display hardware has consumed all the 525 * buffers attached to this commit call and buffer is ready for reuse 526 * for primary and external. For writeback case, it triggers it when 527 * output buffer is ready for consumer. 528 */ 529 int release_fence; 530 531 /* 532 * Left_roi is optional configuration. Client configures it only when 533 * partial update is enabled. It defines the "region of interest" on 534 * left part of panel when it is split display. For non-split display, 535 * it defines the "region of interest" on the panel. 536 */ 537 struct mdp_rect left_roi; 538 539 /* 540 * Right_roi is optional configuration. Client configures it only when 541 * partial update is enabled. It defines the "region of interest" on 542 * right part of panel for split display configuration. It is not 543 * required for non-split display. 544 */ 545 struct mdp_rect right_roi; 546 547 /* Pointer to a list of input layers for composition. */ 548 struct mdp_input_layer *input_layers; 549 550 /* Input layer count present in input list */ 551 uint32_t input_layer_cnt; 552 553 /* 554 * Output layer for writeback display. It supports only one 555 * layer as output layer. This is not required for primary 556 * and external displays 557 */ 558 struct mdp_output_layer *output_layer; 559 560 /* 561 * This is an output parameter. 562 * 563 * Frame buffer device provides retire fence handle if 564 * COMMIT_RETIRE_FENCE flag is set in commit call. It triggers 565 * retire fence when current layers are swapped with new layers 566 * on display hardware. For video mode panel and writeback, 567 * retire fence and release fences are triggered at the same 568 * time while command mode panel triggers release fence first 569 * (on pingpong done) and retire fence (on rdptr done) 570 * after that. 571 */ 572 int retire_fence; 573 574 /* 575 * Scaler data and control for setting up destination scaler. 576 * A userspace pointer that points to a list of 577 * struct mdp_destination_scaler_data. 578 */ 579 void *dest_scaler; 580 581 /* 582 * Represents number of Destination scaler data provied by userspace. 583 */ 584 uint32_t dest_scaler_cnt; 585 586 /* Backlight level that would update when display commit */ 587 uint32_t bl_level; 588 589 /* 32-bits reserved value for future usage. */ 590 uint32_t reserved[MDP_LAYER_COMMIT_V1_PAD]; 591 }; 592 593 /* 594 * mdp_overlay_list - argument for ioctl MSMFB_ATOMIC_COMMIT 595 */ 596 struct mdp_layer_commit { 597 /* 598 * 32bit version indicates the commit structure selection 599 * from union. Lower 16bits indicates the minor version while 600 * higher 16bits indicates the major version. It selects the 601 * commit structure based on major version selection. Minor version 602 * indicates that reserved fields are in use. 603 * 604 * Current supported version is 1.0 (Major:1 Minor:0) 605 */ 606 uint32_t version; 607 union { 608 /* Layer commit/validate definition for V1 */ 609 struct mdp_layer_commit_v1 commit_v1; 610 }; 611 }; 612 613 struct mdp_point { 614 uint32_t x; 615 uint32_t y; 616 }; 617 618 /* 619 * Async updatable layers. One layer holds configuration for one pipe. 620 */ 621 struct mdp_async_layer { 622 /* 623 * Flag to enable/disable properties for layer configuration. Refer 624 * layer flag config section for all possible flags. 625 */ 626 uint32_t flags; 627 628 /* 629 * Pipe selection for this layer by client. Client provides the 630 * pipe index that the device reserved during ATOMIC_COMMIT. 631 */ 632 uint32_t pipe_ndx; 633 634 /* Source start x,y. */ 635 struct mdp_point src; 636 637 /* Destination start x,y. */ 638 struct mdp_point dst; 639 640 /* 641 * This is an output parameter. 642 * 643 * Frame buffer device sets error code based on the failure. 644 */ 645 int error_code; 646 647 uint32_t reserved[3]; 648 }; 649 650 /* 651 * mdp_position_update - argument for ioctl MSMFB_ASYNC_POSITION_UPDATE 652 */ 653 struct mdp_position_update { 654 /* Pointer to a list of async updatable input layers */ 655 struct mdp_async_layer *input_layers; 656 657 /* Input layer count present in input list */ 658 uint32_t input_layer_cnt; 659 }; 660 661 #define MAX_DET_CURVES 3 662 struct mdp_det_enhance_data { 663 uint32_t enable; 664 int16_t sharpen_level1; 665 int16_t sharpen_level2; 666 uint16_t clip; 667 uint16_t limit; 668 uint16_t thr_quiet; 669 uint16_t thr_dieout; 670 uint16_t thr_low; 671 uint16_t thr_high; 672 uint16_t prec_shift; 673 int16_t adjust_a[MAX_DET_CURVES]; 674 int16_t adjust_b[MAX_DET_CURVES]; 675 int16_t adjust_c[MAX_DET_CURVES]; 676 }; 677 678 /* Flags to enable Scaler and its sub components */ 679 #define ENABLE_SCALE 0x1 680 #define ENABLE_DETAIL_ENHANCE 0x2 681 #define ENABLE_DIRECTION_DETECTION 0x4 682 683 /* LUT configuration flags */ 684 #define SCALER_LUT_SWAP 0x1 685 #define SCALER_LUT_DIR_WR 0x2 686 #define SCALER_LUT_Y_CIR_WR 0x4 687 #define SCALER_LUT_UV_CIR_WR 0x8 688 #define SCALER_LUT_Y_SEP_WR 0x10 689 #define SCALER_LUT_UV_SEP_WR 0x20 690 691 /* Y/RGB and UV filter configuration */ 692 #define FILTER_EDGE_DIRECTED_2D 0x0 693 #define FILTER_CIRCULAR_2D 0x1 694 #define FILTER_SEPARABLE_1D 0x2 695 #define FILTER_BILINEAR 0x3 696 697 /* Alpha filters */ 698 #define FILTER_ALPHA_DROP_REPEAT 0x0 699 #define FILTER_ALPHA_BILINEAR 0x1 700 701 /** 702 * struct mdp_scale_data_v2 703 * Driver uses this new Data structure for storing all scaling params 704 * This structure contains all pixel extension data and QSEED3 filter 705 * configuration and coefficient table indices 706 */ 707 struct mdp_scale_data_v2 { 708 uint32_t enable; 709 710 /* Init phase values */ 711 int32_t init_phase_x[MAX_PLANES]; 712 int32_t phase_step_x[MAX_PLANES]; 713 int32_t init_phase_y[MAX_PLANES]; 714 int32_t phase_step_y[MAX_PLANES]; 715 716 /* This should be set to toal horizontal pixels 717 * left + right + width 718 */ 719 uint32_t num_ext_pxls_left[MAX_PLANES]; 720 721 /* Unused param for backward compatibility */ 722 uint32_t num_ext_pxls_right[MAX_PLANES]; 723 724 /* This should be set to vertical pixels 725 * top + bottom + height 726 */ 727 uint32_t num_ext_pxls_top[MAX_PLANES]; 728 729 /* Unused param for backward compatibility */ 730 uint32_t num_ext_pxls_btm[MAX_PLANES]; 731 732 /* over fetch pixels */ 733 int32_t left_ftch[MAX_PLANES]; 734 int32_t left_rpt[MAX_PLANES]; 735 int32_t right_ftch[MAX_PLANES]; 736 int32_t right_rpt[MAX_PLANES]; 737 738 /* Repeat pixels */ 739 uint32_t top_rpt[MAX_PLANES]; 740 uint32_t btm_rpt[MAX_PLANES]; 741 uint32_t top_ftch[MAX_PLANES]; 742 uint32_t btm_ftch[MAX_PLANES]; 743 744 uint32_t roi_w[MAX_PLANES]; 745 746 /* alpha plane can only be scaled using bilinear or pixel 747 * repeat/drop, specify these for Y and UV planes only 748 */ 749 uint32_t preload_x[MAX_PLANES]; 750 uint32_t preload_y[MAX_PLANES]; 751 uint32_t src_width[MAX_PLANES]; 752 uint32_t src_height[MAX_PLANES]; 753 754 uint32_t dst_width; 755 uint32_t dst_height; 756 757 uint32_t y_rgb_filter_cfg; 758 uint32_t uv_filter_cfg; 759 uint32_t alpha_filter_cfg; 760 uint32_t blend_cfg; 761 762 uint32_t lut_flag; 763 uint32_t dir_lut_idx; 764 765 /* for Y(RGB) and UV planes*/ 766 uint32_t y_rgb_cir_lut_idx; 767 uint32_t uv_cir_lut_idx; 768 uint32_t y_rgb_sep_lut_idx; 769 uint32_t uv_sep_lut_idx; 770 771 struct mdp_det_enhance_data detail_enhance; 772 773 /* reserved value for future usage. */ 774 uint64_t reserved[8]; 775 }; 776 777 /** 778 * struct mdp_scale_luts_info 779 * This struct pointer is received as payload in SET_CFG_IOCTL when the flags 780 * is set to MDP_QSEED3_LUT_CFG 781 * @dir_lut: Direction detection coefficients table 782 * @cir_lut: Circular coefficeints table 783 * @sep_lut: Separable coefficeints table 784 * @dir_lut_size: Size of direction coefficients table 785 * @cir_lut_size: Size of circular coefficients table 786 * @sep_lut_size: Size of separable coefficients table 787 */ 788 struct mdp_scale_luts_info { 789 uint64_t dir_lut; 790 uint64_t cir_lut; 791 uint64_t sep_lut; 792 uint32_t dir_lut_size; 793 uint32_t cir_lut_size; 794 uint32_t sep_lut_size; 795 }; 796 797 #define MDP_QSEED3_LUT_CFG 0x1 798 799 struct mdp_set_cfg { 800 uint64_t flags; 801 uint32_t len; 802 uint64_t payload; 803 }; 804 805 #define HDR_PRIMARIES_COUNT 3 806 807 #define MDP_HDR_STREAM 808 809 struct mdp_hdr_stream { 810 uint32_t eotf; 811 uint32_t display_primaries_x[HDR_PRIMARIES_COUNT]; 812 uint32_t display_primaries_y[HDR_PRIMARIES_COUNT]; 813 uint32_t white_point_x; 814 uint32_t white_point_y; 815 uint32_t max_luminance; 816 uint32_t min_luminance; 817 uint32_t max_content_light_level; 818 uint32_t max_average_light_level; 819 /* DP related */ 820 uint32_t pixel_encoding; 821 uint32_t colorimetry; 822 uint32_t range; 823 uint32_t bits_per_component; 824 uint32_t content_type; 825 uint32_t reserved[5]; 826 }; 827 828 /* hdr hdmi state takes possible values of 1, 2 and 4 respectively */ 829 #define HDR_ENABLE (1 << 0) 830 #define HDR_DISABLE (1 << 1) 831 #define HDR_RESET (1 << 2) 832 833 /* 834 * HDR Control 835 * This encapsulates the HDR metadata as well as a state control 836 * for the HDR metadata as required by the HDMI spec to send the 837 * relevant metadata depending on the state of the HDR playback. 838 * hdr_state: Controls HDR state, takes values HDR_ENABLE, HDR_DISABLE 839 * and HDR_RESET. 840 * hdr_meta: Metadata sent by the userspace for the HDR clip. 841 */ 842 843 struct mdp_hdr_stream_ctrl { 844 __u8 hdr_state; /* HDR state */ 845 struct mdp_hdr_stream hdr_stream; /* HDR metadata */ 846 }; 847 848 #endif 849