1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20(size_t elements,const float * input,float * output,float * sum,float max)18 void xnn_f32_raddstoreexpminusmax_ukernel__neon_p5_x20(
19 size_t elements,
20 const float* input,
21 float* output,
22 float* sum,
23 float max) XNN_DISABLE_TSAN
24 {
25 assert(elements % sizeof(float) == 0);
26
27 const float32x4_t vmagic_bias = vmovq_n_f32(0x1.8000FEp23f);
28 // The smallest x for which expf(x) is normalized.
29 const float32x4_t vdenorm_cutoff = vmovq_n_f32(-0x1.5D589Ep6f);
30 const float32x4_t vlog2e = vmovq_n_f32(0x1.715476p+0f);
31 // Last 7 bits are zeroes
32 const float32x4_t vminus_ln2_hi = vmovq_n_f32(-0x1.62E400p-1f);
33 const float32x4_t vminus_ln2_lo = vmovq_n_f32(-0x1.7F7D1Cp-20f);
34
35 const float32x4_t vc1 = vmovq_n_f32(0x1.FFFFF6p-1f);
36 const float32x4_t vc2 = vmovq_n_f32(0x1.FFFDC6p-2f);
37 const float32x4_t vc3 = vmovq_n_f32(0x1.555A80p-3f);
38 const float32x4_t vc4 = vmovq_n_f32(0x1.573A1Ap-5f);
39 const float32x4_t vc5 = vmovq_n_f32(0x1.0F9F9Cp-7f);
40
41 const float32x4_t vi_max = vdupq_n_f32(max);
42
43 float32x4_t vacc0 = vmovq_n_f32(0.0f);
44 for (; elements >= 20 * sizeof(float); elements -= 20 * sizeof(float)) {
45 // Load 20 (5x4) inputs at a time.
46 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
47 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
48 const float32x4_t vi89AB = vld1q_f32(input); input += 4;
49 const float32x4_t viCDEF = vld1q_f32(input); input += 4;
50 const float32x4_t viGHIJ = vld1q_f32(input); input += 4;
51
52 // Subtract maximum input x := i - i_max. This implies x <= 0.
53 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
54 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
55 const float32x4_t vx89AB = vsubq_f32(vi89AB, vi_max);
56 const float32x4_t vxCDEF = vsubq_f32(viCDEF, vi_max);
57 const float32x4_t vxGHIJ = vsubq_f32(viGHIJ, vi_max);
58
59 // Compute reduced argument n := round(x / log(2)).
60 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
61 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
62 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
63 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
64 // of the algorithm.
65 float32x4_t vn0123 = vmlaq_f32(vmagic_bias, vx0123, vlog2e);
66 float32x4_t vn4567 = vmlaq_f32(vmagic_bias, vx4567, vlog2e);
67 float32x4_t vn89AB = vmlaq_f32(vmagic_bias, vx89AB, vlog2e);
68 float32x4_t vnCDEF = vmlaq_f32(vmagic_bias, vxCDEF, vlog2e);
69 float32x4_t vnGHIJ = vmlaq_f32(vmagic_bias, vxGHIJ, vlog2e);
70
71 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
72 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
73 const float32x4_t vs0123 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn0123), 23));
74 const float32x4_t vs4567 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn4567), 23));
75 const float32x4_t vs89AB = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn89AB), 23));
76 const float32x4_t vsCDEF = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vnCDEF), 23));
77 const float32x4_t vsGHIJ = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vnGHIJ), 23));
78
79 // Subtract the large number back to get final n := round(x / log(2)).
80 vn0123 = vsubq_f32(vn0123, vmagic_bias);
81 vn4567 = vsubq_f32(vn4567, vmagic_bias);
82 vn89AB = vsubq_f32(vn89AB, vmagic_bias);
83 vnCDEF = vsubq_f32(vnCDEF, vmagic_bias);
84 vnGHIJ = vsubq_f32(vnGHIJ, vmagic_bias);
85
86 // Compute reduced argument t := z - n * log(2).
87 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
88 float32x4_t vt0123 = vmlaq_f32(vx0123, vn0123, vminus_ln2_hi);
89 float32x4_t vt4567 = vmlaq_f32(vx4567, vn4567, vminus_ln2_hi);
90 float32x4_t vt89AB = vmlaq_f32(vx89AB, vn89AB, vminus_ln2_hi);
91 float32x4_t vtCDEF = vmlaq_f32(vxCDEF, vnCDEF, vminus_ln2_hi);
92 float32x4_t vtGHIJ = vmlaq_f32(vxGHIJ, vnGHIJ, vminus_ln2_hi);
93
94 vt0123 = vmlaq_f32(vt0123, vn0123, vminus_ln2_lo);
95 vt4567 = vmlaq_f32(vt4567, vn4567, vminus_ln2_lo);
96 vt89AB = vmlaq_f32(vt89AB, vn89AB, vminus_ln2_lo);
97 vtCDEF = vmlaq_f32(vtCDEF, vnCDEF, vminus_ln2_lo);
98 vtGHIJ = vmlaq_f32(vtGHIJ, vnGHIJ, vminus_ln2_lo);
99
100 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
101 float32x4_t vp0123 = vmlaq_f32(vc4, vc5, vt0123);
102 float32x4_t vp4567 = vmlaq_f32(vc4, vc5, vt4567);
103 float32x4_t vp89AB = vmlaq_f32(vc4, vc5, vt89AB);
104 float32x4_t vpCDEF = vmlaq_f32(vc4, vc5, vtCDEF);
105 float32x4_t vpGHIJ = vmlaq_f32(vc4, vc5, vtGHIJ);
106
107 vp0123 = vmlaq_f32(vc3, vp0123, vt0123);
108 vp4567 = vmlaq_f32(vc3, vp4567, vt4567);
109 vp89AB = vmlaq_f32(vc3, vp89AB, vt89AB);
110 vpCDEF = vmlaq_f32(vc3, vpCDEF, vtCDEF);
111 vpGHIJ = vmlaq_f32(vc3, vpGHIJ, vtGHIJ);
112
113 vp0123 = vmlaq_f32(vc2, vp0123, vt0123);
114 vp4567 = vmlaq_f32(vc2, vp4567, vt4567);
115 vp89AB = vmlaq_f32(vc2, vp89AB, vt89AB);
116 vpCDEF = vmlaq_f32(vc2, vpCDEF, vtCDEF);
117 vpGHIJ = vmlaq_f32(vc2, vpGHIJ, vtGHIJ);
118
119 vp0123 = vmlaq_f32(vc1, vp0123, vt0123);
120 vp4567 = vmlaq_f32(vc1, vp4567, vt4567);
121 vp89AB = vmlaq_f32(vc1, vp89AB, vt89AB);
122 vpCDEF = vmlaq_f32(vc1, vpCDEF, vtCDEF);
123 vpGHIJ = vmlaq_f32(vc1, vpGHIJ, vtGHIJ);
124
125 // Reconstruct the final f value:
126 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
127 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
128 // = s + (t * s) * p
129 vt0123 = vmulq_f32(vt0123, vs0123);
130 vt4567 = vmulq_f32(vt4567, vs4567);
131 vt89AB = vmulq_f32(vt89AB, vs89AB);
132 vtCDEF = vmulq_f32(vtCDEF, vsCDEF);
133 vtGHIJ = vmulq_f32(vtGHIJ, vsGHIJ);
134
135 float32x4_t vf0123 = vmlaq_f32(vs0123, vp0123, vt0123);
136 float32x4_t vf4567 = vmlaq_f32(vs4567, vp4567, vt4567);
137 float32x4_t vf89AB = vmlaq_f32(vs89AB, vp89AB, vt89AB);
138 float32x4_t vfCDEF = vmlaq_f32(vsCDEF, vpCDEF, vtCDEF);
139 float32x4_t vfGHIJ = vmlaq_f32(vsGHIJ, vpGHIJ, vtGHIJ);
140
141 // For inputs below denormal cutoff, replace output with +0.0f.
142 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
143 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
144 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
145 vf89AB = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf89AB), vcltq_f32(vx89AB, vdenorm_cutoff)));
146 vfCDEF = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfCDEF), vcltq_f32(vxCDEF, vdenorm_cutoff)));
147 vfGHIJ = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfGHIJ), vcltq_f32(vxGHIJ, vdenorm_cutoff)));
148
149 // Store 20 (5x4) outputs at a time.
150 vst1q_f32(output, vf0123); output += 4;
151 vst1q_f32(output, vf4567); output += 4;
152 vst1q_f32(output, vf89AB); output += 4;
153 vst1q_f32(output, vfCDEF); output += 4;
154 vst1q_f32(output, vfGHIJ); output += 4;
155
156 // Accumulate computed exponents.
157 vacc0 = vaddq_f32(vacc0, vf0123);
158 vacc0 = vaddq_f32(vacc0, vf4567);
159 vacc0 = vaddq_f32(vacc0, vf89AB);
160 vacc0 = vaddq_f32(vacc0, vfCDEF);
161 vacc0 = vaddq_f32(vacc0, vfGHIJ);
162 }
163
164 float32x4_t vacc = vacc0;
165 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
166 // Load 4 inputs at a time.
167 const float32x4_t vi = vld1q_f32(input); input += 4;
168
169 // Subtract maximum input x := i - i_max. This implies x <= 0.
170 const float32x4_t vx = vsubq_f32(vi, vi_max);
171
172 // Compute reduced argument n := round(x / log(2)).
173 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
174 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
175 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
176 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
177 // of the algorithm.
178 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
179
180 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
181 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
182 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
183
184 // Subtract the large number back to get final n := round(x / log(2)).
185 vn = vsubq_f32(vn, vmagic_bias);
186
187 // Compute reduced argument t := z - n * log(2).
188 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
189 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
190 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
191
192 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
193 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
194 vp = vmlaq_f32(vc3, vp, vt);
195 vp = vmlaq_f32(vc2, vp, vt);
196 vp = vmlaq_f32(vc1, vp, vt);
197
198 // Reconstruct the final f value:
199 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
200 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
201 // = s + (t * s) * p
202 vt = vmulq_f32(vt, vs);
203 float32x4_t vf = vmlaq_f32(vs, vp, vt);
204
205 // For inputs below denormal cutoff, replace output with +0.0f.
206 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
207 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
208
209 // Store 4 outputs at a time.
210 vst1q_f32(output, vf); output += 4;
211
212 // Accumulate computed exponents.
213 vacc = vaddq_f32(vacc, vf);
214 }
215 #if XNN_ARCH_ARM64
216 float vacc_lo = vaddvq_f32(vacc);
217 #else
218 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
219 #endif
220 if (elements != 0) {
221 assert(elements >= 1 * sizeof(float));
222 assert(elements <= 3 * sizeof(float));
223 // Load 4 inputs at a time.
224 const float32x4_t vi = vld1q_f32(input); input += 4;
225
226 // Subtract maximum input x := i - i_max. This implies x <= 0.
227 const float32x4_t vx = vsubq_f32(vi, vi_max);
228
229 // Compute reduced argument n := round(x / log(2)).
230 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
231 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
232 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
233 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
234 // of the algorithm.
235 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
236
237 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
238 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
239 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
240
241 // Subtract the large number back to get final n := round(x / log(2)).
242 vn = vsubq_f32(vn, vmagic_bias);
243
244 // Compute reduced argument t := z - n * log(2).
245 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
246 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
247 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
248
249 // Compute degree-5 polynomial approximation for exp(t) on [-log(2)/2, log(2)/2].
250 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
251 vp = vmlaq_f32(vc3, vp, vt);
252 vp = vmlaq_f32(vc2, vp, vt);
253 vp = vmlaq_f32(vc1, vp, vt);
254
255 // Reconstruct the final f value:
256 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
257 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
258 // = s + (t * s) * p
259 vt = vmulq_f32(vt, vs);
260 float32x4_t vf = vmlaq_f32(vs, vp, vt);
261
262 // For inputs below denormal cutoff, replace output with +0.0f.
263 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
264 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
265
266 float32x2_t vf_lo = vget_low_f32(vf);
267 if (elements & (2 * sizeof(float))) {
268 // Store 2 outputs at a time.
269 vst1_f32(output, vf_lo); output += 2;
270
271 // Accumulate 2 computed exponents.
272 #if XNN_ARCH_ARM64
273 vacc_lo += vaddv_f32(vf_lo);
274 #else
275 vacc_lo = vadd_f32(vacc_lo, vf_lo);
276 #endif
277
278 vf_lo = vget_high_f32(vf);
279 }
280 if (elements & (1 * sizeof(float))) {
281 // Store 1 output at a time.
282 vst1_lane_f32(output, vf_lo, 0);
283
284 // Accumulate 1 computed exponent.
285 #if XNN_ARCH_ARM64
286 vacc_lo += vget_lane_f32(vf_lo, 0);
287 #else
288 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
289 #endif
290 }
291 }
292 // Reduce 4 elements in the SIMD register
293 #if XNN_ARCH_ARM64
294 *sum = vacc_lo;
295 #else
296 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
297 #endif
298 }
299