1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <el3_common_macros.S> 11 12 .globl bl2_entrypoint 13 .globl bl2_run_next_image 14 15 16func bl2_entrypoint 17 /* Save arguments x0-x3 from previous Boot loader */ 18 mov r9, r0 19 mov r10, r1 20 mov r11, r2 21 mov r12, r3 22 23 el3_entrypoint_common \ 24 _init_sctlr=1 \ 25 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 26 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 27 _init_memory=1 \ 28 _init_c_runtime=1 \ 29 _exception_vectors=bl2_vector_table 30 31 /* 32 * Restore parameters of boot rom 33 */ 34 mov r0, r9 35 mov r1, r10 36 mov r2, r11 37 mov r3, r12 38 39 /* --------------------------------------------- 40 * Perform BL2 setup 41 * --------------------------------------------- 42 */ 43 bl bl2_el3_setup 44 45 /* --------------------------------------------- 46 * Jump to main function. 47 * --------------------------------------------- 48 */ 49 bl bl2_main 50 51 /* --------------------------------------------- 52 * Should never reach this point. 53 * --------------------------------------------- 54 */ 55 no_ret plat_panic_handler 56 57endfunc bl2_entrypoint 58 59func bl2_run_next_image 60 mov r8,r0 61 62 /* 63 * MMU needs to be disabled because both BL2 and BL32 execute 64 * in PL1, and therefore share the same address space. 65 * BL32 will initialize the address space according to its 66 * own requirement. 67 */ 68 bl disable_mmu_icache_secure 69 stcopr r0, TLBIALL 70 dsb sy 71 isb 72 mov r0, r8 73 bl bl2_el3_plat_prepare_exit 74 75 /* 76 * Extract PC and SPSR based on struct `entry_point_info_t` 77 * and load it in LR and SPSR registers respectively. 78 */ 79 ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] 80 ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] 81 msr spsr_xc, r1 82 83 /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ 84 cps #MODE32_svc 85 ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET] 86 cps #MODE32_mon 87 88 add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET 89 ldm r8, {r0, r1, r2, r3} 90 exception_return 91endfunc bl2_run_next_image 92