1Advisory TFV-7 (CVE-2018-3639) 2============================== 3 4+----------------+-------------------------------------------------------------+ 5| Title | Trusted Firmware-A exposure to cache speculation | 6| | vulnerability Variant 4 | 7+================+=============================================================+ 8| CVE ID | `CVE-2018-3639`_ | 9+----------------+-------------------------------------------------------------+ 10| Date | 21 May 2018 (Updated 7 June 2018) | 11+----------------+-------------------------------------------------------------+ 12| Versions | All, up to and including v1.5 | 13| Affected | | 14+----------------+-------------------------------------------------------------+ 15| Configurations | All | 16| Affected | | 17+----------------+-------------------------------------------------------------+ 18| Impact | Leakage of secure world data to normal world | 19+----------------+-------------------------------------------------------------+ 20| Fix Version | `Pull Request #1392`_, `Pull Request #1397`_ | 21+----------------+-------------------------------------------------------------+ 22| Credit | Google | 23+----------------+-------------------------------------------------------------+ 24 25This security advisory describes the current understanding of the Trusted 26Firmware-A (TF-A) exposure to Variant 4 of the cache speculation vulnerabilities 27identified by `Google Project Zero`_. To understand the background and wider 28impact of these vulnerabilities on Arm systems, please refer to the `Arm 29Processor Security Update`_. 30 31At the time of writing, the TF-A project is not aware of a Variant 4 exploit 32that could be used against TF-A. It is likely to be very difficult to achieve an 33exploit against current standard configurations of TF-A, due to the limited 34interfaces into the secure world with attacker-controlled inputs. However, this 35is becoming increasingly difficult to guarantee with the introduction of complex 36new firmware interfaces, for example the `Software Delegated Exception Interface 37(SDEI)`_. Also, the TF-A project does not have visibility of all 38vendor-supplied interfaces. Therefore, the TF-A project takes a conservative 39approach by mitigating Variant 4 in hardware wherever possible during secure 40world execution. The mitigation is enabled by setting an implementation defined 41control bit to prevent the re-ordering of stores and loads. 42 43For each affected CPU type, TF-A implements one of the two following mitigation 44approaches in `Pull Request #1392`_ and `Pull Request #1397`_. Both approaches 45have a system performance impact, which varies for each CPU type and use-case. 46The mitigation code is enabled by default, but can be disabled at compile time 47for platforms that are unaffected or where the risk is deemed low enough. 48 49Arm CPUs not mentioned below are unaffected. 50 51Static mitigation 52----------------- 53 54For affected CPUs, this approach enables the mitigation during EL3 55initialization, following every PE reset. No mechanism is provided to disable 56the mitigation at runtime. 57 58This approach permanently mitigates the entire software stack and no additional 59mitigation code is required in other software components. 60 61TF-A implements this approach for the following affected CPUs: 62 63- Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of 64 ``CPUACTLR_EL1`` (``S3_1_C15_C2_0``). 65 66- Cortex-A73, by setting bit 3 of ``S3_0_C15_C0_0`` (not documented in the 67 Technical Reference Manual (TRM)). 68 69- Cortex-A75, by setting bit 35 (reserved in TRM) of ``CPUACTLR_EL1`` 70 (``S3_0_C15_C1_0``). 71 72Dynamic mitigation 73------------------ 74 75For affected CPUs, this approach also enables the mitigation during EL3 76initialization, following every PE reset. In addition, this approach implements 77``SMCCC_ARCH_WORKAROUND_2`` in the Arm architectural range to allow callers at 78lower exception levels to temporarily disable the mitigation in their execution 79context, where the risk is deemed low enough. This approach enables mitigation 80on entry to EL3, and restores the mitigation state of the lower exception level 81on exit from EL3. For more information on this approach, see `Firmware 82interfaces for mitigating cache speculation vulnerabilities`_. 83 84This approach may be complemented by additional mitigation code in other 85software components, for example code that calls ``SMCCC_ARCH_WORKAROUND_2``. 86However, even without any mitigation code in other software components, this 87approach will effectively permanently mitigate the entire software stack, since 88the default mitigation state for firmware-managed execution contexts is enabled. 89 90Since the expectation in this approach is that more software executes with the 91mitigation disabled, this may result in better system performance than the 92static approach for some systems or use-cases. However, for other systems or 93use-cases, this performance saving may be outweighed by the additional overhead 94of ``SMCCC_ARCH_WORKAROUND_2`` calls and TF-A exception handling. 95 96TF-A implements this approach for the following affected CPU: 97 98- Cortex-A76, by setting and clearing bit 16 (reserved in TRM) of 99 ``CPUACTLR2_EL1`` (``S3_0_C15_C1_1``). 100 101.. _Google Project Zero: https://bugs.chromium.org/p/project-zero/issues/detail?id=1528 102.. _Arm Processor Security Update: http://www.arm.com/security-update 103.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 104.. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf 105.. _Firmware interfaces for mitigating cache speculation vulnerabilities: https://developer.arm.com/cache-speculation-vulnerability-firmware-specification 106.. _Pull Request #1392: https://github.com/ARM-software/arm-trusted-firmware/pull/1392 107.. _Pull Request #1397: https://github.com/ARM-software/arm-trusted-firmware/pull/1397 108