1 /* 2 * Copyright (c) 2019, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <drivers/arm/scu.h> 9 #include <lib/mmio.h> 10 #include <plat/common/platform.h> 11 #include <stdint.h> 12 13 /******************************************************************************* 14 * Turn ON snoop control unit. This is needed to synchronize the data between 15 * CPU's. 16 ******************************************************************************/ enable_snoop_ctrl_unit(uintptr_t base)17void enable_snoop_ctrl_unit(uintptr_t base) 18 { 19 uint32_t scu_ctrl; 20 21 INFO("[SCU]: enabling snoop control unit ... \n"); 22 23 assert(base != 0U); 24 scu_ctrl = mmio_read_32(base + SCU_CTRL_REG); 25 26 /* already enabled? */ 27 if ((scu_ctrl & SCU_ENABLE_BIT) != 0) { 28 return; 29 } 30 31 scu_ctrl |= SCU_ENABLE_BIT; 32 mmio_write_32(base + SCU_CTRL_REG, scu_ctrl); 33 } 34 35 /******************************************************************************* 36 * Snoop Control Unit configuration register. This is read-only register and 37 * contains information such as 38 * - number of CPUs present 39 * - is a particular CPU operating in SMP mode or AMP mode 40 * - data cache size of a particular CPU 41 * - does SCU has ACP port 42 * - is L2CPRESENT 43 * NOTE: user of this API should interpert the bits in this register according 44 * to the TRM 45 ******************************************************************************/ read_snoop_ctrl_unit_cfg(uintptr_t base)46uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base) 47 { 48 assert(base != 0U); 49 50 return mmio_read_32(base + SCU_CFG_REG); 51 } 52