1 /*
2 * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <lib/mmio.h>
9 #include <lib/utils_def.h>
10
11 #include "avs_driver.h"
12 #include "cpg_registers.h"
13 #include "rcar_def.h"
14 #include "rcar_private.h"
15
16 #if (AVS_SETTING_ENABLE == 1)
17 #if PMIC_ROHM_BD9571
18 /* Read PMIC register for debug. 1:enable / 0:disable */
19 #define AVS_READ_PMIC_REG_ENABLE 0
20 /* The re-try number of times of the AVS setting. */
21 #define AVS_RETRY_NUM (1U)
22 #endif /* PMIC_ROHM_BD9571 */
23
24 /* Base address of Adaptive Voltage Scaling module registers*/
25 #define AVS_BASE (0xE60A0000U)
26 /* Adaptive Dynamic Voltage ADJust Parameter2 registers */
27 #define ADVADJP2 (AVS_BASE + 0x013CU)
28
29 /* Mask VOLCOND bit in ADVADJP2 registers */
30 #define ADVADJP2_VOLCOND_MASK (0x000001FFU) /* VOLCOND[8:0] */
31
32 #if PMIC_ROHM_BD9571
33 /* I2C for DVFS bit in CPG registers for module standby and software reset*/
34 #define CPG_SYS_DVFS_BIT (0x04000000U)
35 #endif /* PMIC_ROHM_BD9571 */
36 /* ADVFS Module bit in CPG registers for module standby and software reset*/
37 #define CPG_SYS_ADVFS_BIT (0x02000000U)
38
39 #if PMIC_ROHM_BD9571
40 /* Base address of IICDVFS registers*/
41 #define IIC_DVFS_BASE (0xE60B0000U)
42 /* IIC bus data register */
43 #define IIC_ICDR (IIC_DVFS_BASE + 0x0000U)
44 /* IIC bus control register */
45 #define IIC_ICCR (IIC_DVFS_BASE + 0x0004U)
46 /* IIC bus status register */
47 #define IIC_ICSR (IIC_DVFS_BASE + 0x0008U)
48 /* IIC interrupt control register */
49 #define IIC_ICIC (IIC_DVFS_BASE + 0x000CU)
50 /* IIC clock control register low */
51 #define IIC_ICCL (IIC_DVFS_BASE + 0x0010U)
52 /* IIC clock control register high */
53 #define IIC_ICCH (IIC_DVFS_BASE + 0x0014U)
54
55 /* Bit in ICSR register */
56 #define ICSR_BUSY (0x10U)
57 #define ICSR_AL (0x08U)
58 #define ICSR_TACK (0x04U)
59 #define ICSR_WAIT (0x02U)
60 #define ICSR_DTE (0x01U)
61
62 /* Bit in ICIC register */
63 #define ICIC_TACKE (0x04U)
64 #define ICIC_WAITE (0x02U)
65 #define ICIC_DTEE (0x01U)
66
67 /* I2C bus interface enable */
68 #define ICCR_ENABLE (0x80U)
69 /* Start condition */
70 #define ICCR_START (0x94U)
71 /* Stop condition */
72 #define ICCR_STOP (0x90U)
73 /* Restart condition with change to receive mode change */
74 #define ICCR_START_RECV (0x81U)
75 /* Stop condition for receive mode */
76 #define ICCR_STOP_RECV (0xC0U)
77
78 /* Low-level period of SCL */
79 #define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */
80 #define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */
81 #define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */
82 #define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */
83 /* High-level period of SCL */
84 #define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */
85 #define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */
86 #define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */
87 #define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */
88
89 /* PMIC */
90 /* ROHM BD9571 slave address + (W) */
91 #define PMIC_W_SLAVE_ADDRESS (0x60U)
92 /* ROHM BD9571 slave address + (R) */
93 #define PMIC_R_SLAVE_ADDRESS (0x61U)
94 /* ROHM BD9571 DVFS SetVID register */
95 #define PMIC_DVFS_SETVID (0x54U)
96 #endif /* PMIC_ROHM_BD9571 */
97
98 /* Individual information */
99 #define EFUSE_AVS0 (0U)
100 #define EFUSE_AVS_NUM ARRAY_SIZE(init_vol_tbl)
101
102 typedef struct {
103 uint32_t avs; /* AVS code */
104 uint8_t vol; /* Voltage */
105 } initial_voltage_t;
106
107 static const initial_voltage_t init_vol_tbl[] = {
108 /* AVS code, ROHM BD9571 DVFS SetVID register */
109 {0x00U, 0x53U}, /* AVS0, 0.83V */
110 {0x01U, 0x52U}, /* AVS1, 0.82V */
111 {0x02U, 0x51U}, /* AVS2, 0.81V */
112 {0x04U, 0x50U}, /* AVS3, 0.80V */
113 {0x08U, 0x4FU}, /* AVS4, 0.79V */
114 {0x10U, 0x4EU}, /* AVS5, 0.78V */
115 {0x20U, 0x4DU}, /* AVS6, 0.77V */
116 {0x40U, 0x4CU} /* AVS7, 0.76V */
117 };
118
119 #if PMIC_ROHM_BD9571
120 /* Kind of AVS settings status */
121 typedef enum {
122 avs_status_none = 0,
123 avs_status_init,
124 avs_status_start_condition,
125 avs_status_set_slave_addr,
126 avs_status_write_reg_addr,
127 avs_status_write_reg_data,
128 avs_status_stop_condition,
129 avs_status_end,
130 avs_status_complete,
131 avs_status_al_start,
132 avs_status_al_transfer,
133 avs_status_nack,
134 avs_status_error_stop,
135 ave_status_error_end
136 } avs_status_t;
137
138 /* Kind of AVS error */
139 typedef enum {
140 avs_error_none = 0,
141 avs_error_al,
142 avs_error_nack
143 } avs_error_t;
144
145 static avs_status_t avs_status;
146 static uint32_t avs_retry;
147 #endif /* PMIC_ROHM_BD9571 */
148 static uint32_t efuse_avs = EFUSE_AVS0;
149
150 #if PMIC_ROHM_BD9571
151 /* prototype */
152 static avs_error_t avs_check_error(void);
153 static void avs_set_iic_clock(void);
154 #if AVS_READ_PMIC_REG_ENABLE == 1
155 static uint8_t avs_read_pmic_reg(uint8_t addr);
156 static void avs_poll(uint8_t bit_pos, uint8_t val);
157 #endif
158 #endif /* PMIC_ROHM_BD9571 */
159 #endif /* (AVS_SETTING_ENABLE==1) */
160
161 /*
162 * Initialize to enable the AVS setting.
163 */
rcar_avs_init(void)164 void rcar_avs_init(void)
165 {
166 #if (AVS_SETTING_ENABLE == 1)
167 uint32_t val;
168
169 #if PMIC_ROHM_BD9571
170 /* Initialize AVS status */
171 avs_status = avs_status_init;
172 #endif /* PMIC_ROHM_BD9571 */
173
174 /* Enable clock supply to ADVFS. */
175 mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, CPG_SYS_ADVFS_BIT);
176
177 /* Read AVS code (Initial values are derived from eFuse) */
178 val = mmio_read_32(ADVADJP2) & ADVADJP2_VOLCOND_MASK;
179
180 for (efuse_avs = 0U; efuse_avs < EFUSE_AVS_NUM; efuse_avs++) {
181 if (val == init_vol_tbl[efuse_avs].avs)
182 break;
183 }
184
185 if (efuse_avs >= EFUSE_AVS_NUM)
186 efuse_avs = EFUSE_AVS0; /* Not applicable */
187 #if PMIC_ROHM_BD9571
188 /* Enable clock supply to DVFS. */
189 mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, CPG_SYS_DVFS_BIT);
190
191 /* Disable I2C module and All internal registers initialized. */
192 mmio_write_8(IIC_ICCR, 0x00U);
193 while ((mmio_read_8(IIC_ICCR) & ICCR_ENABLE) != 0U) {
194 /* Disable I2C module and all internal registers initialized. */
195 mmio_write_8(IIC_ICCR, 0x00U);
196 }
197
198 /* Set next status */
199 avs_status = avs_status_start_condition;
200
201 #endif /* PMIC_ROHM_BD9571 */
202 #endif /* (AVS_SETTING_ENABLE==1) */
203 }
204
205 /*
206 * Set the value of register corresponding to the voltage
207 * by transfer of I2C to PIMC.
208 */
rcar_avs_setting(void)209 void rcar_avs_setting(void)
210 {
211 #if (AVS_SETTING_ENABLE == 1)
212 #if PMIC_ROHM_BD9571
213 avs_error_t err;
214
215 switch (avs_status) {
216 case avs_status_start_condition:
217 /* Set ICCR.ICE=1 to activate the I2C module. */
218 mmio_write_8(IIC_ICCR, mmio_read_8(IIC_ICCR) | ICCR_ENABLE);
219 /* Set frequency of 400kHz */
220 avs_set_iic_clock();
221 /* Set ICIC.TACKE=1, ICIC.WAITE=1, ICIC.DTEE=1 to */
222 /* enable interrupt control. */
223 mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC)
224 | ICIC_TACKE | ICIC_WAITE | ICIC_DTEE);
225 /* Write H'94 in ICCR to issue start condition */
226 mmio_write_8(IIC_ICCR, ICCR_START);
227 /* Set next status */
228 avs_status = avs_status_set_slave_addr;
229 break;
230 case avs_status_set_slave_addr:
231 /* Check error. */
232 err = avs_check_error();
233 if (err == avs_error_al) {
234 /* Recovery sequence of just after start. */
235 avs_status = avs_status_al_start;
236 } else if (err == avs_error_nack) {
237 /* Recovery sequence of detected NACK */
238 avs_status = avs_status_nack;
239 } else {
240 /* Was data transmission enabled ? */
241 if ((mmio_read_8(IIC_ICSR) & ICSR_DTE) == ICSR_DTE) {
242 /* Clear ICIC.DTEE to disable a DTE interrupt */
243 mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC)
244 & (uint8_t) (~ICIC_DTEE));
245 /* Send PMIC slave address + (W) */
246 mmio_write_8(IIC_ICDR, PMIC_W_SLAVE_ADDRESS);
247 /* Set next status */
248 avs_status = avs_status_write_reg_addr;
249 }
250 }
251 break;
252 case avs_status_write_reg_addr:
253 /* Check error. */
254 err = avs_check_error();
255 if (err == avs_error_al) {
256 /* Recovery sequence of during data transfer. */
257 avs_status = avs_status_al_transfer;
258 } else if (err == avs_error_nack) {
259 /* Recovery sequence of detected NACK */
260 avs_status = avs_status_nack;
261 } else {
262 /* If wait state after data transmission. */
263 if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {
264 /* Write PMIC DVFS_SetVID address */
265 mmio_write_8(IIC_ICDR, PMIC_DVFS_SETVID);
266 /* Clear ICSR.WAIT to exit from wait state. */
267 mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
268 & (uint8_t) (~ICSR_WAIT));
269 /* Set next status */
270 avs_status = avs_status_write_reg_data;
271 }
272 }
273 break;
274 case avs_status_write_reg_data:
275 /* Check error. */
276 err = avs_check_error();
277 if (err == avs_error_al) {
278 /* Recovery sequence of during data transfer. */
279 avs_status = avs_status_al_transfer;
280 } else if (err == avs_error_nack) {
281 /* Recovery sequence of detected NACK */
282 avs_status = avs_status_nack;
283 } else {
284 /* If wait state after data transmission. */
285 if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {
286 /* Dose efuse_avs exceed the number of */
287 /* the tables? */
288 if (efuse_avs >= EFUSE_AVS_NUM) {
289 ERROR("%s%s=%u\n", "AVS number of ",
290 "eFuse is out of range. number",
291 efuse_avs);
292 /* Infinite loop */
293 panic();
294 }
295 /* Write PMIC DVFS_SetVID value */
296 mmio_write_8(IIC_ICDR,
297 init_vol_tbl[efuse_avs].vol);
298 /* Clear ICSR.WAIT to exit from wait state. */
299 mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
300 & (uint8_t) (~ICSR_WAIT));
301 /* Set next status */
302 avs_status = avs_status_stop_condition;
303 }
304 }
305 break;
306 case avs_status_stop_condition:
307 err = avs_check_error();
308 if (err == avs_error_al) {
309 /* Recovery sequence of during data transfer. */
310 avs_status = avs_status_al_transfer;
311 } else if (err == avs_error_nack) {
312 /* Recovery sequence of detected NACK */
313 avs_status = avs_status_nack;
314 } else {
315 /* If wait state after data transmission. */
316 if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {
317 /* Write H'90 in ICCR to issue stop condition */
318 mmio_write_8(IIC_ICCR, ICCR_STOP);
319 /* Clear ICSR.WAIT to exit from wait state. */
320 mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
321 & (uint8_t) (~ICSR_WAIT));
322 /* Set next status */
323 avs_status = avs_status_end;
324 }
325 }
326 break;
327 case avs_status_end:
328 /* Is this module not busy?. */
329 if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) {
330 /* Set ICCR=H'00 to disable the I2C module. */
331 mmio_write_8(IIC_ICCR, 0x00U);
332 /* Set next status */
333 avs_status = avs_status_complete;
334 }
335 break;
336 case avs_status_al_start:
337 /* Clear ICSR.AL bit */
338 mmio_write_8(IIC_ICSR, (mmio_read_8(IIC_ICSR)
339 & (uint8_t) (~ICSR_AL)));
340 /* Transmit a clock pulse */
341 mmio_write_8(IIC_ICDR, init_vol_tbl[EFUSE_AVS0].vol);
342 /* Set next status */
343 avs_status = avs_status_error_stop;
344 break;
345 case avs_status_al_transfer:
346 /* Clear ICSR.AL bit */
347 mmio_write_8(IIC_ICSR, (mmio_read_8(IIC_ICSR)
348 & (uint8_t) (~ICSR_AL)));
349 /* Set next status */
350 avs_status = avs_status_error_stop;
351 break;
352 case avs_status_nack:
353 /* Write H'90 in ICCR to issue stop condition */
354 mmio_write_8(IIC_ICCR, ICCR_STOP);
355 /* Disable a WAIT and DTEE interrupt. */
356 mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC)
357 & (uint8_t) (~(ICIC_WAITE | ICIC_DTEE)));
358 /* Clear ICSR.TACK bit */
359 mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
360 & (uint8_t) (~ICSR_TACK));
361 /* Set next status */
362 avs_status = ave_status_error_end;
363 break;
364 case avs_status_error_stop:
365 /* If wait state after data transmission. */
366 if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {
367 /* Write H'90 in ICCR to issue stop condition */
368 mmio_write_8(IIC_ICCR, ICCR_STOP);
369 /* Clear ICSR.WAIT to exit from wait state. */
370 mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
371 & (uint8_t) (~ICSR_WAIT));
372 /* Set next status */
373 avs_status = ave_status_error_end;
374 }
375 break;
376 case ave_status_error_end:
377 /* Is this module not busy?. */
378 if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) {
379 /* Set ICCR=H'00 to disable the I2C module. */
380 mmio_write_8(IIC_ICCR, 0x00U);
381 /* Increment the re-try number of times. */
382 avs_retry++;
383 /* Set start a re-try to status. */
384 avs_status = avs_status_start_condition;
385 }
386 break;
387 case avs_status_complete:
388 /* After "avs_status" became the "avs_status_complete", */
389 /* "avs_setting()" function may be called. */
390 break;
391 default:
392 /* This case is not possible. */
393 ERROR("AVS setting is in invalid status. status=%u\n",
394 avs_status);
395 /* Infinite loop */
396 panic();
397 break;
398 }
399 #endif /* PMIC_ROHM_BD9571 */
400 #endif /* (AVS_SETTING_ENABLE==1) */
401 }
402
403 /*
404 * Finish the AVS setting.
405 */
rcar_avs_end(void)406 void rcar_avs_end(void)
407 {
408 #if (AVS_SETTING_ENABLE == 1)
409 uint32_t mstp;
410
411 #if PMIC_ROHM_BD9571
412 /* While status is not completion, be repeated. */
413 while (avs_status != avs_status_complete)
414 rcar_avs_setting();
415
416 NOTICE("AVS setting succeeded. DVFS_SetVID=0x%x\n",
417 init_vol_tbl[efuse_avs].vol);
418
419 #if AVS_READ_PMIC_REG_ENABLE == 1
420 {
421 uint8_t addr = PMIC_DVFS_SETVID;
422 uint8_t value = avs_read_pmic_reg(addr);
423
424 NOTICE("Read PMIC register. address=0x%x value=0x%x\n",
425 addr, value);
426 }
427 #endif
428
429 /* Bit of the module which wants to disable clock supply. */
430 mstp = CPG_SYS_DVFS_BIT;
431 /* Disables the supply of clock signal to a module. */
432 cpg_write(CPG_SMSTPCR9, mmio_read_32(CPG_SMSTPCR9) | mstp);
433 #endif /* PMIC_ROHM_BD9571 */
434
435 /* Bit of the module which wants to disable clock supply. */
436 mstp = CPG_SYS_ADVFS_BIT;
437 /* Disables the supply of clock signal to a module. */
438 cpg_write(CPG_SMSTPCR9, mmio_read_32(CPG_SMSTPCR9) | mstp);
439
440 #endif /* (AVS_SETTING_ENABLE==1) */
441 }
442
443 #if (AVS_SETTING_ENABLE == 1)
444 #if PMIC_ROHM_BD9571
445 /*
446 * Check error and judge re-try.
447 */
avs_check_error(void)448 static avs_error_t avs_check_error(void)
449 {
450 avs_error_t ret;
451
452 if ((mmio_read_8(IIC_ICSR) & ICSR_AL) == ICSR_AL) {
453 NOTICE("%s AVS status=%d Retry=%u\n",
454 "Loss of arbitration is detected.", avs_status, avs_retry);
455 /* Check of retry number of times */
456 if (avs_retry >= AVS_RETRY_NUM) {
457 ERROR("AVS setting failed in retry. max=%u\n",
458 AVS_RETRY_NUM);
459 /* Infinite loop */
460 panic();
461 }
462 /* Set the error detected to error status. */
463 ret = avs_error_al;
464 } else if ((mmio_read_8(IIC_ICSR) & ICSR_TACK) == ICSR_TACK) {
465 NOTICE("%s AVS status=%d Retry=%u\n",
466 "Non-acknowledge is detected.", avs_status, avs_retry);
467 /* Check of retry number of times */
468 if (avs_retry >= AVS_RETRY_NUM) {
469 ERROR("AVS setting failed in retry. max=%u\n",
470 AVS_RETRY_NUM);
471 /* Infinite loop */
472 panic();
473 }
474 /* Set the error detected to error status. */
475 ret = avs_error_nack;
476 } else {
477 /* Not error. */
478 ret = avs_error_none;
479 }
480 return ret;
481 }
482
483 /*
484 * Set I2C for DVFS clock.
485 */
avs_set_iic_clock(void)486 static void avs_set_iic_clock(void)
487 {
488 uint32_t md_pin;
489
490 /* Read Mode pin register. */
491 md_pin = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
492 /* Set the module clock (CP phy) for the IIC-DVFS. */
493 /* CP phy is EXTAL / 2. */
494 switch (md_pin) {
495 case MD14_MD13_TYPE_0: /* EXTAL = 16.6666MHz */
496 mmio_write_8(IIC_ICCL, ICCL_FREQ_8p33M);
497 mmio_write_8(IIC_ICCH, ICCH_FREQ_8p33M);
498 break;
499 case MD14_MD13_TYPE_1: /* EXTAL = 20MHz */
500 mmio_write_8(IIC_ICCL, ICCL_FREQ_10M);
501 mmio_write_8(IIC_ICCH, ICCH_FREQ_10M);
502 break;
503 case MD14_MD13_TYPE_2: /* EXTAL = 25MHz (H3/M3) */
504 mmio_write_8(IIC_ICCL, ICCL_FREQ_12p5M);
505 mmio_write_8(IIC_ICCH, ICCH_FREQ_12p5M);
506 break;
507 case MD14_MD13_TYPE_3: /* EXTAL = 33.3333MHz */
508 mmio_write_8(IIC_ICCL, ICCL_FREQ_16p66M);
509 mmio_write_8(IIC_ICCH, ICCH_FREQ_16p66M);
510 break;
511 default: /* This case is not possible. */
512 /* CP Phy frequency is to be set for the 16.66MHz */
513 mmio_write_8(IIC_ICCL, ICCL_FREQ_16p66M);
514 mmio_write_8(IIC_ICCH, ICCH_FREQ_16p66M);
515 break;
516 }
517 }
518
519 #if AVS_READ_PMIC_REG_ENABLE == 1
520 /*
521 * Read the value of the register of PMIC.
522 */
avs_read_pmic_reg(uint8_t addr)523 static uint8_t avs_read_pmic_reg(uint8_t addr)
524 {
525 uint8_t reg;
526
527 /* Set ICCR.ICE=1 to activate the I2C module. */
528 mmio_write_8(IIC_ICCR, mmio_read_8(IIC_ICCR) | ICCR_ENABLE);
529
530 /* Set frequency of 400kHz */
531 avs_set_iic_clock();
532
533 /*
534 * Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission
535 * interrupt and wait interrupt.
536 */
537 mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_WAITE | ICIC_DTEE);
538
539 /* Write H'94 in ICCR to issue start condition */
540 mmio_write_8(IIC_ICCR, ICCR_START);
541
542 /* Wait for a until ICSR.DTE becomes 1. */
543 avs_poll(ICSR_DTE, 1U);
544
545 /* Clear ICIC.DTEE to disable a DTE interrupt. */
546 mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t) (~ICIC_DTEE));
547 /* Send slave address of PMIC */
548 mmio_write_8(IIC_ICDR, PMIC_W_SLAVE_ADDRESS);
549
550 /* Wait for a until ICSR.WAIT becomes 1. */
551 avs_poll(ICSR_WAIT, 1U);
552
553 /* write PMIC address */
554 mmio_write_8(IIC_ICDR, addr);
555 /* Clear ICSR.WAIT to exit from WAIT status. */
556 mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));
557
558 /* Wait for a until ICSR.WAIT becomes 1. */
559 avs_poll(ICSR_WAIT, 1U);
560
561 /* Write H'94 in ICCR to issue restart condition */
562 mmio_write_8(IIC_ICCR, ICCR_START);
563 /* Clear ICSR.WAIT to exit from WAIT status. */
564 mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));
565 /* Set ICIC.DTEE=1 to enable data transmission interrupt. */
566 mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_DTEE);
567
568 /* Wait for a until ICSR.DTE becomes 1. */
569 avs_poll(ICSR_DTE, 1U);
570
571 /* Clear ICIC.DTEE to disable a DTE interrupt. */
572 mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t) (~ICIC_DTEE));
573 /* Send slave address of PMIC */
574 mmio_write_8(IIC_ICDR, PMIC_R_SLAVE_ADDRESS);
575
576 /* Wait for a until ICSR.WAIT becomes 1. */
577 avs_poll(ICSR_WAIT, 1U);
578
579 /* Write H'81 to ICCR to issue the repeated START condition */
580 /* for changing the transmission mode to the receive mode. */
581 mmio_write_8(IIC_ICCR, ICCR_START_RECV);
582 /* Clear ICSR.WAIT to exit from WAIT status. */
583 mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));
584
585 /* Wait for a until ICSR.WAIT becomes 1. */
586 avs_poll(ICSR_WAIT, 1U);
587
588 /* Set ICCR to H'C0 for the STOP condition */
589 mmio_write_8(IIC_ICCR, ICCR_STOP_RECV);
590 /* Clear ICSR.WAIT to exit from WAIT status. */
591 mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));
592 /* Set ICIC.DTEE=1 to enable data transmission interrupt. */
593 mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_DTEE);
594
595 /* Wait for a until ICSR.DTE becomes 1. */
596 avs_poll(ICSR_DTE, 1U);
597
598 /* Receive DVFS SetVID register */
599 /* Clear ICIC.DTEE to disable a DTE interrupt. */
600 mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t) (~ICIC_DTEE));
601 /* Receive DVFS SetVID register */
602 reg = mmio_read_8(IIC_ICDR);
603
604 /* Wait until ICSR.BUSY is cleared. */
605 avs_poll(ICSR_BUSY, 0U);
606
607 /* Set ICCR=H'00 to disable the I2C module. */
608 mmio_write_8(IIC_ICCR, 0x00U);
609
610 return reg;
611 }
612
613 /*
614 * Wait processing by the polling.
615 */
avs_poll(uint8_t bit_pos,uint8_t val)616 static void avs_poll(uint8_t bit_pos, uint8_t val)
617 {
618 uint8_t bit_val = 0U;
619
620 if (val != 0U)
621 bit_val = bit_pos;
622
623 while (1) {
624 if ((mmio_read_8(IIC_ICSR) & bit_pos) == bit_val)
625 break;
626 }
627 }
628 #endif /* AVS_READ_PMIC_REG_ENABLE */
629 #endif /* PMIC_ROHM_BD9571 */
630 #endif /* (AVS_SETTING_ENABLE==1) */
631