1// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) 2/* 3 * Copyright (c) 2020, Arm Limited. All rights reserved. 4 * 5 * Devicetree for the Arm Ltd. FPGA platform 6 * Number and kind of CPU cores differs from image to image, so the 7 * topology is auto-detected by BL31, and the /cpus node is created and 8 * populated accordingly at runtime. 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/dts-v1/; 14 15/ { 16 model = "ARM FPGA"; 17 compatible = "arm,fpga", "arm,vexpress"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &dbg_uart; 24 }; 25 26 chosen { 27 stdout-path = "serial0:38400n8"; 28 bootargs = "console=ttyAMA0,38400n8 earlycon"; 29 /* Allow to upload a generous 100MB initrd payload. */ 30 linux,initrd-start = <0x0 0x84000000>; 31 linux,initrd-end = <0x0 0x85400000>; 32 }; 33 34 /* /cpus node will be added by BL31 at runtime. */ 35 36 psci { 37 compatible = "arm,psci-0.2"; 38 method = "smc"; 39 }; 40 41 timer { 42 compatible = "arm,armv8-timer"; 43 clock-frequency = <10000000>; 44 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 45 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 46 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 47 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 48 }; 49 50 pmu { 51 compatible = "arm,armv8-pmuv3"; 52 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 53 }; 54 55 /* This node will be removed at runtime on cores without SPE. */ 56 spe-pmu { 57 compatible = "arm,statistical-profiling-extension-v1"; 58 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 59 }; 60 61 memory@80000000 { 62 device_type = "memory"; 63 reg = <0x0 0x80000000 0x0 0x80000000>, 64 <0x8 0x80000000 0x1 0x80000000>; 65 }; 66 67 68 bus_refclk: refclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <100000000>; 72 clock-output-names = "apb_pclk"; 73 }; 74 75 uartclk: baudclock { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <10000000>; 79 clock-output-names = "uartclk"; 80 }; 81 82 dbg_uart: serial@7ff80000 { 83 compatible = "arm,pl011", "arm,primecell"; 84 reg = <0x0 0x7ff80000 0x0 0x00001000>; 85 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 86 clocks = <&uartclk>, <&bus_refclk>; 87 clock-names = "uartclk", "apb_pclk"; 88 }; 89 90 gic: interrupt-controller@30000000 { 91 compatible = "arm,gic-v3"; 92 #address-cells = <2>; 93 #interrupt-cells = <3>; 94 #size-cells = <2>; 95 ranges; 96 interrupt-controller; 97 reg = <0x0 0x30000000 0x0 0x00010000>, /* GICD */ 98 /* The GICR size will be adjusted at runtime to match the cores. */ 99 <0x0 0x30040000 0x0 0x00020000>; /* GICR for one core */ 100 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 101 }; 102}; 103