1/* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache and unified L2 cache 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a72_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * --------------------------------------------- 28 */ 29func cortex_a72_disable_l2_prefetch 30 mrs x0, CORTEX_A72_ECTLR_EL1 31 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 32 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 33 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 34 bic x0, x0, x1 35 msr CORTEX_A72_ECTLR_EL1, x0 36 isb 37 ret 38endfunc cortex_a72_disable_l2_prefetch 39 40 /* --------------------------------------------- 41 * Disable the load-store hardware prefetcher. 42 * --------------------------------------------- 43 */ 44func cortex_a72_disable_hw_prefetcher 45 mrs x0, CORTEX_A72_CPUACTLR_EL1 46 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 47 msr CORTEX_A72_CPUACTLR_EL1, x0 48 isb 49 dsb ish 50 ret 51endfunc cortex_a72_disable_hw_prefetcher 52 53 /* --------------------------------------------- 54 * Disable intra-cluster coherency 55 * --------------------------------------------- 56 */ 57func cortex_a72_disable_smp 58 mrs x0, CORTEX_A72_ECTLR_EL1 59 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 60 msr CORTEX_A72_ECTLR_EL1, x0 61 ret 62endfunc cortex_a72_disable_smp 63 64 /* --------------------------------------------- 65 * Disable debug interfaces 66 * --------------------------------------------- 67 */ 68func cortex_a72_disable_ext_debug 69 mov x0, #1 70 msr osdlr_el1, x0 71 isb 72 dsb sy 73 ret 74endfunc cortex_a72_disable_ext_debug 75 76 /* -------------------------------------------------- 77 * Errata Workaround for Cortex A72 Errata #859971. 78 * This applies only to revision <= r0p3 of Cortex A72. 79 * Inputs: 80 * x0: variant[4:7] and revision[0:3] of current cpu. 81 * Shall clobber: 82 * -------------------------------------------------- 83 */ 84func errata_a72_859971_wa 85 mov x17,x30 86 bl check_errata_859971 87 cbz x0, 1f 88 mrs x1, CORTEX_A72_CPUACTLR_EL1 89 orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 90 msr CORTEX_A72_CPUACTLR_EL1, x1 911: 92 ret x17 93endfunc errata_a72_859971_wa 94 95func check_errata_859971 96 mov x1, #0x03 97 b cpu_rev_var_ls 98endfunc check_errata_859971 99 100func check_errata_cve_2017_5715 101 cpu_check_csv2 x0, 1f 102#if WORKAROUND_CVE_2017_5715 103 mov x0, #ERRATA_APPLIES 104#else 105 mov x0, #ERRATA_MISSING 106#endif 107 ret 1081: 109 mov x0, #ERRATA_NOT_APPLIES 110 ret 111endfunc check_errata_cve_2017_5715 112 113func check_errata_cve_2018_3639 114#if WORKAROUND_CVE_2018_3639 115 mov x0, #ERRATA_APPLIES 116#else 117 mov x0, #ERRATA_MISSING 118#endif 119 ret 120endfunc check_errata_cve_2018_3639 121 122 /* -------------------------------------------------- 123 * Errata workaround for Cortex A72 Errata #1319367. 124 * This applies to all revisions of Cortex A72. 125 * -------------------------------------------------- 126 */ 127func check_errata_1319367 128#if ERRATA_A72_1319367 129 mov x0, #ERRATA_APPLIES 130#else 131 mov x0, #ERRATA_MISSING 132#endif 133 ret 134endfunc check_errata_1319367 135 136 /* ------------------------------------------------- 137 * The CPU Ops reset function for Cortex-A72. 138 * ------------------------------------------------- 139 */ 140func cortex_a72_reset_func 141 mov x19, x30 142 bl cpu_get_rev_var 143 mov x18, x0 144 145#if ERRATA_A72_859971 146 mov x0, x18 147 bl errata_a72_859971_wa 148#endif 149 150#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 151 cpu_check_csv2 x0, 1f 152 adr x0, wa_cve_2017_5715_mmu_vbar 153 msr vbar_el3, x0 154 /* isb will be performed before returning from this function */ 1551: 156#endif 157 158#if WORKAROUND_CVE_2018_3639 159 mrs x0, CORTEX_A72_CPUACTLR_EL1 160 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 161 msr CORTEX_A72_CPUACTLR_EL1, x0 162 isb 163 dsb sy 164#endif 165 166 /* --------------------------------------------- 167 * Enable the SMP bit. 168 * --------------------------------------------- 169 */ 170 mrs x0, CORTEX_A72_ECTLR_EL1 171 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 172 msr CORTEX_A72_ECTLR_EL1, x0 173 isb 174 ret x19 175endfunc cortex_a72_reset_func 176 177 /* ---------------------------------------------------- 178 * The CPU Ops core power down function for Cortex-A72. 179 * ---------------------------------------------------- 180 */ 181func cortex_a72_core_pwr_dwn 182 mov x18, x30 183 184 /* --------------------------------------------- 185 * Turn off caches. 186 * --------------------------------------------- 187 */ 188 bl cortex_a72_disable_dcache 189 190 /* --------------------------------------------- 191 * Disable the L2 prefetches. 192 * --------------------------------------------- 193 */ 194 bl cortex_a72_disable_l2_prefetch 195 196 /* --------------------------------------------- 197 * Disable the load-store hardware prefetcher. 198 * --------------------------------------------- 199 */ 200 bl cortex_a72_disable_hw_prefetcher 201 202 /* --------------------------------------------- 203 * Flush L1 caches. 204 * --------------------------------------------- 205 */ 206 mov x0, #DCCISW 207 bl dcsw_op_level1 208 209 /* --------------------------------------------- 210 * Come out of intra cluster coherency 211 * --------------------------------------------- 212 */ 213 bl cortex_a72_disable_smp 214 215 /* --------------------------------------------- 216 * Force the debug interfaces to be quiescent 217 * --------------------------------------------- 218 */ 219 mov x30, x18 220 b cortex_a72_disable_ext_debug 221endfunc cortex_a72_core_pwr_dwn 222 223 /* ------------------------------------------------------- 224 * The CPU Ops cluster power down function for Cortex-A72. 225 * ------------------------------------------------------- 226 */ 227func cortex_a72_cluster_pwr_dwn 228 mov x18, x30 229 230 /* --------------------------------------------- 231 * Turn off caches. 232 * --------------------------------------------- 233 */ 234 bl cortex_a72_disable_dcache 235 236 /* --------------------------------------------- 237 * Disable the L2 prefetches. 238 * --------------------------------------------- 239 */ 240 bl cortex_a72_disable_l2_prefetch 241 242 /* --------------------------------------------- 243 * Disable the load-store hardware prefetcher. 244 * --------------------------------------------- 245 */ 246 bl cortex_a72_disable_hw_prefetcher 247 248#if !SKIP_A72_L1_FLUSH_PWR_DWN 249 /* --------------------------------------------- 250 * Flush L1 caches. 251 * --------------------------------------------- 252 */ 253 mov x0, #DCCISW 254 bl dcsw_op_level1 255#endif 256 257 /* --------------------------------------------- 258 * Disable the optional ACP. 259 * --------------------------------------------- 260 */ 261 bl plat_disable_acp 262 263 /* ------------------------------------------------- 264 * Flush the L2 caches. 265 * ------------------------------------------------- 266 */ 267 mov x0, #DCCISW 268 bl dcsw_op_level2 269 270 /* --------------------------------------------- 271 * Come out of intra cluster coherency 272 * --------------------------------------------- 273 */ 274 bl cortex_a72_disable_smp 275 276 /* --------------------------------------------- 277 * Force the debug interfaces to be quiescent 278 * --------------------------------------------- 279 */ 280 mov x30, x18 281 b cortex_a72_disable_ext_debug 282endfunc cortex_a72_cluster_pwr_dwn 283 284#if REPORT_ERRATA 285/* 286 * Errata printing function for Cortex A72. Must follow AAPCS. 287 */ 288func cortex_a72_errata_report 289 stp x8, x30, [sp, #-16]! 290 291 bl cpu_get_rev_var 292 mov x8, x0 293 294 /* 295 * Report all errata. The revision-variant information is passed to 296 * checking functions of each errata. 297 */ 298 report_errata ERRATA_A72_859971, cortex_a72, 859971 299 report_errata ERRATA_A72_1319367, cortex_a72, 1319367 300 report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 301 report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639 302 303 ldp x8, x30, [sp], #16 304 ret 305endfunc cortex_a72_errata_report 306#endif 307 308 /* --------------------------------------------- 309 * This function provides cortex_a72 specific 310 * register information for crash reporting. 311 * It needs to return with x6 pointing to 312 * a list of register names in ascii and 313 * x8 - x15 having values of registers to be 314 * reported. 315 * --------------------------------------------- 316 */ 317.section .rodata.cortex_a72_regs, "aS" 318cortex_a72_regs: /* The ascii list of register names to be reported */ 319 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 320 321func cortex_a72_cpu_reg_dump 322 adr x6, cortex_a72_regs 323 mrs x8, CORTEX_A72_ECTLR_EL1 324 mrs x9, CORTEX_A72_MERRSR_EL1 325 mrs x10, CORTEX_A72_L2MERRSR_EL1 326 ret 327endfunc cortex_a72_cpu_reg_dump 328 329declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \ 330 cortex_a72_reset_func, \ 331 check_errata_cve_2017_5715, \ 332 CPU_NO_EXTRA2_FUNC, \ 333 cortex_a72_core_pwr_dwn, \ 334 cortex_a72_cluster_pwr_dwn 335