1/* 2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19 20/* -------------------------------------------------- 21 * Errata Workaround for A78 Erratum 1688305. 22 * This applies to revision r0p0 and r1p0 of A78. 23 * Inputs: 24 * x0: variant[4:7] and revision[0:3] of current cpu. 25 * Shall clobber: x0-x17 26 * -------------------------------------------------- 27 */ 28func errata_a78_1688305_wa 29 /* Compare x0 against revision r1p0 */ 30 mov x17, x30 31 bl check_errata_1688305 32 cbz x0, 1f 33 mrs x1, CORTEX_A78_ACTLR2_EL1 34 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1 35 msr CORTEX_A78_ACTLR2_EL1, x1 36 isb 371: 38 ret x17 39endfunc errata_a78_1688305_wa 40 41func check_errata_1688305 42 /* Applies to r0p0 and r1p0 */ 43 mov x1, #0x10 44 b cpu_rev_var_ls 45endfunc check_errata_1688305 46 47 /* -------------------------------------------------- 48 * Errata Workaround for Cortex A78 Errata #1941498. 49 * This applies to revisions r0p0, r1p0, and r1p1. 50 * x0: variant[4:7] and revision[0:3] of current cpu. 51 * Shall clobber: x0-x17 52 * -------------------------------------------------- 53 */ 54func errata_a78_1941498_wa 55 /* Compare x0 against revision <= r1p1 */ 56 mov x17, x30 57 bl check_errata_1941498 58 cbz x0, 1f 59 60 /* Set bit 8 in ECTLR_EL1 */ 61 mrs x1, CORTEX_A78_CPUECTLR_EL1 62 orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8 63 msr CORTEX_A78_CPUECTLR_EL1, x1 64 isb 651: 66 ret x17 67endfunc errata_a78_1941498_wa 68 69func check_errata_1941498 70 /* Check for revision <= r1p1, might need to be updated later. */ 71 mov x1, #0x11 72 b cpu_rev_var_ls 73endfunc check_errata_1941498 74 75 /* -------------------------------------------------- 76 * Errata Workaround for A78 Erratum 1951500. 77 * This applies to revisions r1p0 and r1p1 of A78. 78 * The issue also exists in r0p0 but there is no fix 79 * in that revision. 80 * Inputs: 81 * x0: variant[4:7] and revision[0:3] of current cpu. 82 * Shall clobber: x0-x17 83 * -------------------------------------------------- 84 */ 85func errata_a78_1951500_wa 86 /* Compare x0 against revisions r1p0 - r1p1 */ 87 mov x17, x30 88 bl check_errata_1951500 89 cbz x0, 1f 90 91 msr S3_6_c15_c8_0, xzr 92 ldr x0, =0x10E3900002 93 msr S3_6_c15_c8_2, x0 94 ldr x0, =0x10FFF00083 95 msr S3_6_c15_c8_3, x0 96 ldr x0, =0x2001003FF 97 msr S3_6_c15_c8_1, x0 98 99 mov x0, #1 100 msr S3_6_c15_c8_0, x0 101 ldr x0, =0x10E3800082 102 msr S3_6_c15_c8_2, x0 103 ldr x0, =0x10FFF00083 104 msr S3_6_c15_c8_3, x0 105 ldr x0, =0x2001003FF 106 msr S3_6_c15_c8_1, x0 107 108 mov x0, #2 109 msr S3_6_c15_c8_0, x0 110 ldr x0, =0x10E3800200 111 msr S3_6_c15_c8_2, x0 112 ldr x0, =0x10FFF003E0 113 msr S3_6_c15_c8_3, x0 114 ldr x0, =0x2001003FF 115 msr S3_6_c15_c8_1, x0 116 117 isb 1181: 119 ret x17 120endfunc errata_a78_1951500_wa 121 122func check_errata_1951500 123 /* Applies to revisions r1p0 and r1p1. */ 124 mov x1, #CPU_REV(1, 0) 125 mov x2, #CPU_REV(1, 1) 126 b cpu_rev_var_range 127endfunc check_errata_1951500 128 129 /* ------------------------------------------------- 130 * The CPU Ops reset function for Cortex-A78 131 * ------------------------------------------------- 132 */ 133func cortex_a78_reset_func 134 mov x19, x30 135 bl cpu_get_rev_var 136 mov x18, x0 137 138#if ERRATA_A78_1688305 139 mov x0, x18 140 bl errata_a78_1688305_wa 141#endif 142 143#if ERRATA_A78_1941498 144 mov x0, x18 145 bl errata_a78_1941498_wa 146#endif 147 148#if ERRATA_A78_1951500 149 mov x0, x18 150 bl errata_a78_1951500_wa 151#endif 152 153#if ENABLE_AMU 154 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 155 mrs x0, actlr_el3 156 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 157 msr actlr_el3, x0 158 159 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 160 mrs x0, actlr_el2 161 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 162 msr actlr_el2, x0 163 164 /* Enable group0 counters */ 165 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 166 msr CPUAMCNTENSET0_EL0, x0 167 168 /* Enable group1 counters */ 169 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 170 msr CPUAMCNTENSET1_EL0, x0 171#endif 172 173 isb 174 ret x19 175endfunc cortex_a78_reset_func 176 177 /* --------------------------------------------- 178 * HW will do the cache maintenance while powering down 179 * --------------------------------------------- 180 */ 181func cortex_a78_core_pwr_dwn 182 /* --------------------------------------------- 183 * Enable CPU power down bit in power control register 184 * --------------------------------------------- 185 */ 186 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 187 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 188 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 189 isb 190 ret 191endfunc cortex_a78_core_pwr_dwn 192 193 /* 194 * Errata printing function for cortex_a78. Must follow AAPCS. 195 */ 196#if REPORT_ERRATA 197func cortex_a78_errata_report 198 stp x8, x30, [sp, #-16]! 199 200 bl cpu_get_rev_var 201 mov x8, x0 202 203 /* 204 * Report all errata. The revision-variant information is passed to 205 * checking functions of each errata. 206 */ 207 report_errata ERRATA_A78_1688305, cortex_a78, 1688305 208 report_errata ERRATA_A78_1941498, cortex_a78, 1941498 209 report_errata ERRATA_A78_1951500, cortex_a78, 1951500 210 211 ldp x8, x30, [sp], #16 212 ret 213endfunc cortex_a78_errata_report 214#endif 215 216 /* --------------------------------------------- 217 * This function provides cortex_a78 specific 218 * register information for crash reporting. 219 * It needs to return with x6 pointing to 220 * a list of register names in ascii and 221 * x8 - x15 having values of registers to be 222 * reported. 223 * --------------------------------------------- 224 */ 225.section .rodata.cortex_a78_regs, "aS" 226cortex_a78_regs: /* The ascii list of register names to be reported */ 227 .asciz "cpuectlr_el1", "" 228 229func cortex_a78_cpu_reg_dump 230 adr x6, cortex_a78_regs 231 mrs x8, CORTEX_A78_CPUECTLR_EL1 232 ret 233endfunc cortex_a78_cpu_reg_dump 234 235declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 236 cortex_a78_reset_func, \ 237 cortex_a78_core_pwr_dwn 238