1/* 2 * Copyright (c) 2019-2020, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78_ae.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19 /* ------------------------------------------------- 20 * The CPU Ops reset function for Cortex-A78-AE 21 * ------------------------------------------------- 22 */ 23#if ENABLE_AMU 24func cortex_a78_ae_reset_func 25 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 26 mrs x0, actlr_el3 27 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 28 msr actlr_el3, x0 29 30 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 31 mrs x0, actlr_el2 32 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 33 msr actlr_el2, x0 34 35 /* Enable group0 counters */ 36 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 37 msr CPUAMCNTENSET0_EL0, x0 38 39 /* Enable group1 counters */ 40 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 41 msr CPUAMCNTENSET1_EL0, x0 42 isb 43 44 ret 45endfunc cortex_a78_ae_reset_func 46#endif 47 48 /* ------------------------------------------------------- 49 * HW will do the cache maintenance while powering down 50 * ------------------------------------------------------- 51 */ 52func cortex_a78_ae_core_pwr_dwn 53 /* ------------------------------------------------------- 54 * Enable CPU power down bit in power control register 55 * ------------------------------------------------------- 56 */ 57 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 58 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 59 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 60 isb 61 ret 62endfunc cortex_a78_ae_core_pwr_dwn 63 64 /* 65 * Errata printing function for cortex_a78_ae. Must follow AAPCS. 66 */ 67#if REPORT_ERRATA 68func cortex_a78_ae_errata_report 69 ret 70endfunc cortex_a78_ae_errata_report 71#endif 72 73 /* ------------------------------------------------------- 74 * This function provides cortex_a78_ae specific 75 * register information for crash reporting. 76 * It needs to return with x6 pointing to 77 * a list of register names in ascii and 78 * x8 - x15 having values of registers to be 79 * reported. 80 * ------------------------------------------------------- 81 */ 82.section .rodata.cortex_a78_ae_regs, "aS" 83cortex_a78_ae_regs: /* The ascii list of register names to be reported */ 84 .asciz "cpuectlr_el1", "" 85 86func cortex_a78_ae_cpu_reg_dump 87 adr x6, cortex_a78_ae_regs 88 mrs x8, CORTEX_A78_CPUECTLR_EL1 89 ret 90endfunc cortex_a78_ae_cpu_reg_dump 91 92#if ENABLE_AMU 93#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func 94#else 95#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC 96#endif 97 98declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ 99 A78_AE_RESET_FUNC, \ 100 cortex_a78_ae_core_pwr_dwn 101