1/* 2 * Copyright (c) 2019-2020, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/tbbr/tbbr_img_def.h> 8 9/dts-v1/; 10 11/ { 12 dtb-registry { 13 compatible = "fconf,dyn_cfg-dtb_registry"; 14 15 tb_fw-config { 16 load-address = <0x0 0x4001300>; 17 max-size = <0x1800>; 18 id = <TB_FW_CONFIG_ID>; 19 }; 20 21 hw-config { 22 load-address = <0x0 0x82000000>; 23 max-size = <0x01000000>; 24 id = <HW_CONFIG_ID>; 25 }; 26 27 /* 28 * Load SoC and TOS firmware configs at the base of 29 * non shared SRAM. The runtime checks ensure we don't 30 * overlap BL2, BL31 or BL32. The NT firmware config 31 * is loaded at base of DRAM. 32 */ 33 soc_fw-config { 34 load-address = <0x0 0x04001300>; 35 max-size = <0x200>; 36 id = <SOC_FW_CONFIG_ID>; 37 }; 38 39 tos_fw-config { 40 load-address = <0x0 0x04001500>; 41 max-size = <0xB00>; 42 id = <TOS_FW_CONFIG_ID>; 43 }; 44 45 nt_fw-config { 46 load-address = <0x0 0x80000000>; 47 max-size = <0x200>; 48 id = <NT_FW_CONFIG_ID>; 49 }; 50 }; 51}; 52