1/* 2 * Copyright (c) 2019, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <platform_def.h> 10 11 .globl plat_secondary_cold_boot_setup 12 .globl plat_get_my_entrypoint 13 .globl plat_is_my_cpu_primary 14 15 /* -------------------------------------------------------------------- 16 * void plat_secondary_cold_boot_setup (void); 17 * 18 * For AArch32, cold-booting secondary CPUs is not yet 19 * implemented and they panic. 20 * -------------------------------------------------------------------- 21 */ 22func plat_secondary_cold_boot_setup 23cb_panic: 24 b cb_panic 25endfunc plat_secondary_cold_boot_setup 26 27 /* --------------------------------------------------------------------- 28 * unsigned long plat_get_my_entrypoint (void); 29 * 30 * Main job of this routine is to distinguish between a cold and warm 31 * boot. On FVP, this information can be queried from the power 32 * controller. The Power Control SYS Status Register (PSYSR) indicates 33 * the wake-up reason for the CPU. 34 * 35 * For a cold boot, return 0. 36 * For a warm boot, read the mailbox and return the address it contains. 37 * 38 * TODO: PSYSR is a common register and should be 39 * accessed using locks. Since it is not possible 40 * to use locks immediately after a cold reset 41 * we are relying on the fact that after a cold 42 * reset all cpus will read the same WK field 43 * --------------------------------------------------------------------- 44 */ 45func plat_get_my_entrypoint 46 /* TODO support warm boot */ 47 /* Cold reset */ 48 mov r0, #0 49 bx lr 50 51endfunc plat_get_my_entrypoint 52 53 /* ----------------------------------------------------- 54 * unsigned int plat_is_my_cpu_primary (void); 55 * 56 * Currently configured for a sigle CPU 57 * ----------------------------------------------------- 58 */ 59func plat_is_my_cpu_primary 60 mov r0, #1 61 bx lr 62endfunc plat_is_my_cpu_primary 63