1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a53.h> 11#include <cortex_a57.h> 12#include <cortex_a72.h> 13#include <cpu_macros.S> 14#include <platform_def.h> 15 16 .globl plat_reset_handler 17 .globl plat_arm_calc_core_pos 18 19#define JUNO_REVISION(rev) REV_JUNO_R##rev 20#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev 21#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \ 22 jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision) 23 24 /* -------------------------------------------------------------------- 25 * Helper macro to jump to the given handler if the board revision 26 * matches. 27 * Expects the Juno board revision in x0. 28 * -------------------------------------------------------------------- 29 */ 30 .macro jump_to_handler _revision, _handler 31 cmp r0, #\_revision 32 beq \_handler 33 .endm 34 35 /* -------------------------------------------------------------------- 36 * Platform reset handler for Juno R0. 37 * 38 * Juno R0 has the following topology: 39 * - Quad core Cortex-A53 processor cluster; 40 * - Dual core Cortex-A57 processor cluster. 41 * 42 * This handler does the following: 43 * - Implement workaround for defect id 831273 by enabling an event 44 * stream every 65536 cycles. 45 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 46 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 47 * -------------------------------------------------------------------- 48 */ 49func JUNO_HANDLER(0) 50 /* -------------------------------------------------------------------- 51 * Enable the event stream every 65536 cycles 52 * -------------------------------------------------------------------- 53 */ 54 mov r0, #(0xf << EVNTI_SHIFT) 55 orr r0, r0, #EVNTEN_BIT 56 stcopr r0, CNTKCTL 57 58 /* -------------------------------------------------------------------- 59 * Nothing else to do on Cortex-A53. 60 * -------------------------------------------------------------------- 61 */ 62 jump_if_cpu_midr CORTEX_A53_MIDR, 1f 63 64 /* -------------------------------------------------------------------- 65 * Cortex-A57 specific settings 66 * -------------------------------------------------------------------- 67 */ 68 mov r0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 69 (CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT)) 70 stcopr r0, CORTEX_A57_L2CTLR 711: 72 isb 73 bx lr 74endfunc JUNO_HANDLER(0) 75 76 /* -------------------------------------------------------------------- 77 * Platform reset handler for Juno R1. 78 * 79 * Juno R1 has the following topology: 80 * - Quad core Cortex-A53 processor cluster; 81 * - Dual core Cortex-A57 processor cluster. 82 * 83 * This handler does the following: 84 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 85 * 86 * Note that: 87 * - The default value for the L2 Tag RAM latency for Cortex-A57 is 88 * suitable. 89 * - Defect #831273 doesn't affect Juno R1. 90 * -------------------------------------------------------------------- 91 */ 92func JUNO_HANDLER(1) 93 /* -------------------------------------------------------------------- 94 * Nothing to do on Cortex-A53. 95 * -------------------------------------------------------------------- 96 */ 97 jump_if_cpu_midr CORTEX_A57_MIDR, A57 98 bx lr 99 100A57: 101 /* -------------------------------------------------------------------- 102 * Cortex-A57 specific settings 103 * -------------------------------------------------------------------- 104 */ 105 mov r0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) 106 stcopr r0, CORTEX_A57_L2CTLR 107 isb 108 bx lr 109endfunc JUNO_HANDLER(1) 110 111 /* -------------------------------------------------------------------- 112 * Platform reset handler for Juno R2. 113 * 114 * Juno R2 has the following topology: 115 * - Quad core Cortex-A53 processor cluster; 116 * - Dual core Cortex-A72 processor cluster. 117 * 118 * This handler does the following: 119 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72 120 * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72 121 * 122 * Note that: 123 * - Defect #831273 doesn't affect Juno R2. 124 * -------------------------------------------------------------------- 125 */ 126func JUNO_HANDLER(2) 127 /* -------------------------------------------------------------------- 128 * Nothing to do on Cortex-A53. 129 * -------------------------------------------------------------------- 130 */ 131 jump_if_cpu_midr CORTEX_A72_MIDR, A72 132 bx lr 133 134A72: 135 /* -------------------------------------------------------------------- 136 * Cortex-A72 specific settings 137 * -------------------------------------------------------------------- 138 */ 139 mov r0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 140 (CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT)) 141 stcopr r0, CORTEX_A72_L2CTLR 142 isb 143 bx lr 144endfunc JUNO_HANDLER(2) 145 146 /* -------------------------------------------------------------------- 147 * void plat_reset_handler(void); 148 * 149 * Determine the Juno board revision and call the appropriate reset 150 * handler. 151 * -------------------------------------------------------------------- 152 */ 153func plat_reset_handler 154 /* Read the V2M SYS_ID register */ 155 ldr r0, =(V2M_SYSREGS_BASE + V2M_SYS_ID) 156 ldr r1, [r0] 157 /* Extract board revision from the SYS_ID */ 158 ubfx r0, r1, #V2M_SYS_ID_REV_SHIFT, #4 159 160 JUMP_TO_HANDLER_IF_JUNO_R(0) 161 JUMP_TO_HANDLER_IF_JUNO_R(1) 162 JUMP_TO_HANDLER_IF_JUNO_R(2) 163 164 /* Board revision is not supported */ 165 no_ret plat_panic_handler 166 167endfunc plat_reset_handler 168 169 /* ----------------------------------------------------- 170 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 171 * Helper function to calculate the core position. 172 * ----------------------------------------------------- 173 */ 174func plat_arm_calc_core_pos 175 b css_calc_core_pos_swap_cluster 176endfunc plat_arm_calc_core_pos 177