1# 2# Copyright (c) 2018-2020, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include plat/arm/css/sgi/sgi-common.mk 8 9RDE1EDGE_BASE = plat/arm/board/rde1edge 10 11PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/ 12 13SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S 14 15PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c 16 17BL1_SOURCES += ${SGI_CPU_SOURCES} \ 18 ${RDE1EDGE_BASE}/rde1edge_err.c 19 20BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \ 21 ${RDE1EDGE_BASE}/rde1edge_security.c \ 22 ${RDE1EDGE_BASE}/rde1edge_err.c \ 23 drivers/arm/tzc/tzc_dmc620.c \ 24 lib/utils/mem_region.c \ 25 plat/arm/common/arm_nor_psci_mem_protect.c 26 27BL31_SOURCES += ${SGI_CPU_SOURCES} \ 28 ${RDE1EDGE_BASE}/rde1edge_plat.c \ 29 ${RDE1EDGE_BASE}/rde1edge_topology.c \ 30 drivers/cfi/v2m/v2m_flash.c \ 31 lib/utils/mem_region.c \ 32 plat/arm/common/arm_nor_psci_mem_protect.c 33 34ifeq (${TRUSTED_BOARD_BOOT}, 1) 35BL1_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c 36BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c 37endif 38 39# Add the FDT_SOURCES and options for Dynamic Config 40FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_fw_config.dts \ 41 ${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts 42FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 43TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 44 45# Add the FW_CONFIG to FIP and specify the same to certtool 46$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 47# Add the TB_FW_CONFIG to FIP and specify the same to certtool 48$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 49 50FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts 51NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 52 53# Add the NT_FW_CONFIG to FIP and specify the same to certtool 54$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG})) 55 56ifneq ($(CSS_SGI_CHIP_COUNT),1) 57 $(error "Chip count for RDE1Edge should be 1, currently set to \ 58 ${CSS_SGI_CHIP_COUNT}.") 59endif 60 61override CTX_INCLUDE_AARCH32_REGS := 0 62