1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLAT_SOCFPGA_DEF_H 9 #define PLAT_SOCFPGA_DEF_H 10 11 #include <platform_def.h> 12 13 /* Platform Setting */ 14 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX 15 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 16 17 /* Register Mapping */ 18 #define SOCFPGA_MMC_REG_BASE 0xff808000 19 20 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 21 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 22 23 #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 24 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 25 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 26 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 27 28 #endif /* PLAT_SOCFPGA_DEF_H */ 29 30