1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <common/interrupt_props.h> 13 #include <common/tbbr/tbbr_img_def.h> 14 #include <plat/common/common_def.h> 15 16 #define PLAT_SOCFPGA_STRATIX10 1 17 #define PLAT_SOCFPGA_AGILEX 2 18 19 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 20 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 21 22 /* 23 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 24 * is done and HPS should trigger warm reset via RMR_EL3. 25 */ 26 #define L2_RESET_DONE_REG 0xFFD12218 27 28 /* Magic word to indicate L2 reset is completed */ 29 #define L2_RESET_DONE_STATUS 0x1228E5E7 30 31 /* Define next boot image name and offset */ 32 #define PLAT_NS_IMAGE_OFFSET 0x10000000 33 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 34 35 /******************************************************************************* 36 * Platform binary types for linking 37 ******************************************************************************/ 38 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 39 #define PLATFORM_LINKER_ARCH aarch64 40 41 /* SoCFPGA supports up to 124GB RAM */ 42 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 43 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 44 45 46 /******************************************************************************* 47 * Generic platform constants 48 ******************************************************************************/ 49 #define PLAT_PRIMARY_CPU 0 50 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 51 52 /* Size of cacheable stacks */ 53 #define PLATFORM_STACK_SIZE 0x2000 54 55 /* PSCI related constant */ 56 #define PLAT_NUM_POWER_DOMAINS 5 57 #define PLAT_MAX_PWR_LVL 1 58 #define PLAT_MAX_RET_STATE 1 59 #define PLAT_MAX_OFF_STATE 2 60 #define PLATFORM_SYSTEM_COUNT U(1) 61 #define PLATFORM_CLUSTER_COUNT U(1) 62 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 63 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 64 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 65 PLATFORM_CLUSTER0_CORE_COUNT) 66 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 67 68 /* Interrupt related constant */ 69 70 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 71 72 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 73 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 74 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 75 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 76 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 77 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 78 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 79 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 80 81 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 82 #define TSP_SEC_MEM_BASE BL32_BASE 83 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 84 /******************************************************************************* 85 * Platform memory map related constants 86 ******************************************************************************/ 87 #define DRAM_BASE (0x0) 88 #define DRAM_SIZE (0x80000000) 89 90 #define OCRAM_BASE (0xFFE00000) 91 #define OCRAM_SIZE (0x00040000) 92 93 #define MEM64_BASE (0x0100000000) 94 #define MEM64_SIZE (0x1F00000000) 95 96 #define DEVICE1_BASE (0x80000000) 97 #define DEVICE1_SIZE (0x60000000) 98 99 #define DEVICE2_BASE (0xF7000000) 100 #define DEVICE2_SIZE (0x08E00000) 101 102 #define DEVICE3_BASE (0xFFFC0000) 103 #define DEVICE3_SIZE (0x00008000) 104 105 #define DEVICE4_BASE (0x2000000000) 106 #define DEVICE4_SIZE (0x0100000000) 107 108 /******************************************************************************* 109 * BL31 specific defines. 110 ******************************************************************************/ 111 /* 112 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 113 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 114 * little space for growth. 115 */ 116 117 118 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 119 120 #define BL1_RO_BASE (0xffe00000) 121 #define BL1_RO_LIMIT (0xffe0f000) 122 #define BL1_RW_BASE (0xffe10000) 123 #define BL1_RW_LIMIT (0xffe1ffff) 124 #define BL1_RW_SIZE (0x14000) 125 126 #define BL2_BASE (0xffe00000) 127 #define BL2_LIMIT (0xffe1b000) 128 129 #define BL31_BASE (0x1000) 130 #define BL31_LIMIT (0x81000) 131 132 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 133 134 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 135 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 136 137 #define PLAT_SEC_WARM_ENTRY 0 138 139 /******************************************************************************* 140 * Platform specific page table and MMU setup constants 141 ******************************************************************************/ 142 #define MAX_XLAT_TABLES 8 143 #define MAX_MMAP_REGIONS 16 144 145 /******************************************************************************* 146 * Declarations and constants to access the mailboxes safely. Each mailbox is 147 * aligned on the biggest cache line size in the platform. This is known only 148 * to the platform as it might have a combination of integrated and external 149 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 150 * line at any cache level. They could belong to different cpus/clusters & 151 * get written while being protected by different locks causing corruption of 152 * a valid mailbox address. 153 ******************************************************************************/ 154 #define CACHE_WRITEBACK_SHIFT 6 155 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 156 157 #define PLAT_GIC_BASE (0xFFFC0000) 158 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 159 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 160 #define PLAT_GICR_BASE 0 161 162 /******************************************************************************* 163 * UART related constants 164 ******************************************************************************/ 165 #define PLAT_UART0_BASE (0xFFC02000) 166 #define PLAT_UART1_BASE (0xFFC02100) 167 168 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 169 170 #define PLAT_BAUDRATE (115200) 171 #define PLAT_UART_CLOCK (100000000) 172 173 /******************************************************************************* 174 * PHY related constants 175 ******************************************************************************/ 176 177 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 178 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 179 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 180 181 /******************************************************************************* 182 * System counter frequency related constants 183 ******************************************************************************/ 184 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 185 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) 186 187 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 188 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 189 190 /* 191 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 192 * terminology. On a GICv2 system or mode, the lists will be merged and treated 193 * as Group 0 interrupts. 194 */ 195 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 196 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 197 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 198 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 199 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 200 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 201 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 202 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 203 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 204 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 205 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 206 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 207 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 208 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 209 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 210 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 211 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 212 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 213 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 214 215 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 216 217 #define MAX_IO_HANDLES 4 218 #define MAX_IO_DEVICES 4 219 #define MAX_IO_BLOCK_DEVICES 2 220 221 #ifndef __ASSEMBLER__ 222 struct socfpga_bl31_params { 223 param_header_t h; 224 image_info_t *bl31_image_info; 225 entry_point_info_t *bl32_ep_info; 226 image_info_t *bl32_image_info; 227 entry_point_info_t *bl33_ep_info; 228 image_info_t *bl33_image_info; 229 }; 230 #endif 231 232 #endif /* PLATFORM_DEF_H */ 233 234