1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <endian.h> 8 9 #include <platform_def.h> 10 11 #include <common/debug.h> 12 #include <lib/mmio.h> 13 14 #include "soc.h" 15 16 /* 17 * Get GIC offset 18 * For LS1043a rev1.0, GIC base address align with 4k. 19 * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT] 20 * is set, GIC base address align with 4K, or else align 21 * with 64k. 22 */ get_gic_offset(uint32_t * gicc_base,uint32_t * gicd_base)23void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) 24 { 25 26 uint32_t *ccsr_svr = (uint32_t *)DCFG_CCSR_SVR; 27 uint32_t *gic_align = (uint32_t *)SCFG_GIC400_ALIGN; 28 uint32_t val; 29 uint32_t soc_dev_id; 30 31 val = be32toh(mmio_read_32((uintptr_t)ccsr_svr)); 32 soc_dev_id = val & (SVR_WO_E << 8); 33 34 if ((soc_dev_id == (SVR_LS1043A << 8) || 35 soc_dev_id == (SVR_LS1043AE << 8)) && 36 ((val & 0xff) == REV1_1)) { 37 val = be32toh(mmio_read_32((uintptr_t)gic_align)); 38 if (val & (1U << GIC_ADDR_BIT)) { 39 *gicc_base = GICC_BASE; 40 *gicd_base = GICD_BASE; 41 } else { 42 *gicc_base = GICC_BASE_64K; 43 *gicd_base = GICD_BASE_64K; 44 } 45 } else { 46 *gicc_base = GICC_BASE; 47 *gicd_base = GICD_BASE; 48 } 49 } 50