1 /*
2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/bl_common.h>
10 #include <common/debug.h>
11 #include <common/desc_image_load.h>
12 #include <drivers/generic_delay_timer.h>
13 #include <drivers/ti/uart/uart_16550.h>
14 #include <lib/mmio.h>
15 #include <plat/arm/common/plat_arm.h>
16 #include <plat/common/common_def.h>
17 #include <plat/common/platform.h>
18
19 #include <mcucfg.h>
20 #include <mtcmos.h>
21 #include <mtk_plat_common.h>
22 #include <plat_private.h>
23 #include <spm.h>
24
25 static entry_point_info_t bl32_ep_info;
26 static entry_point_info_t bl33_ep_info;
27
platform_setup_cpu(void)28 static void platform_setup_cpu(void)
29 {
30 /* turn off all the little core's power except cpu 0 */
31 mtcmos_little_cpu_off();
32
33 /* setup big cores */
34 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res,
35 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK |
36 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK |
37 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK |
38 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK |
39 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK);
40 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS);
41 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div,
42 MP1_SW_CG_GEN);
43 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl,
44 MP1_L2RSTDISABLE);
45
46 /* set big cores arm64 boot mode */
47 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg,
48 MP1_CPUCFG_64BIT);
49
50 /* set LITTLE cores arm64 boot mode */
51 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw,
52 MP0_CPUCFG_64BIT);
53
54 /* enable dcm control */
55 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl,
56 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN |
57 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN |
58 INFRACLK_PSYS_DYNAMIC_CG_EN);
59 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl,
60 L2C_SRAM_DCM_EN);
61 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl,
62 MCU_BUS_DCM_EN);
63 }
64
platform_setup_sram(void)65 static void platform_setup_sram(void)
66 {
67 /* protect BL31 memory from non-secure read/write access */
68 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00);
69 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9);
70 }
71
72 /*******************************************************************************
73 * Return a pointer to the 'entry_point_info' structure of the next image for
74 * the security state specified. BL33 corresponds to the non-secure image type
75 * while BL32 corresponds to the secure image type. A NULL pointer is returned
76 * if the image does not exist.
77 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)78 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
79 {
80 entry_point_info_t *next_image_info;
81
82 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
83 assert(next_image_info->h.type == PARAM_EP);
84
85 /* None of the images on this platform can have 0x0 as the entrypoint */
86 if (next_image_info->pc)
87 return next_image_info;
88 else
89 return NULL;
90 }
91
92 /*******************************************************************************
93 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
94 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
95 * are lost (potentially). This needs to be done before the MMU is initialized
96 * so that the memory layout can be used while creating page tables.
97 * BL2 has flushed this information to memory, so we are guaranteed to pick up
98 * good data.
99 ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)100 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
101 u_register_t arg2, u_register_t arg3)
102 {
103 static console_t console;
104
105 console_16550_register(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE, &console);
106
107 VERBOSE("bl31_setup\n");
108
109 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
110 }
111
112 /*******************************************************************************
113 * Perform any BL3-1 platform setup code
114 ******************************************************************************/
bl31_platform_setup(void)115 void bl31_platform_setup(void)
116 {
117 platform_setup_cpu();
118 platform_setup_sram();
119
120 generic_delay_timer_init();
121
122 /* Initialize the gic cpu and distributor interfaces */
123 plat_arm_gic_driver_init();
124 plat_arm_gic_init();
125
126 /* Initialize spm at boot time */
127 spm_boot_init();
128 }
129
130 /*******************************************************************************
131 * Perform the very early platform specific architectural setup here. At the
132 * moment this is only intializes the mmu in a quick and dirty way.
133 ******************************************************************************/
bl31_plat_arch_setup(void)134 void bl31_plat_arch_setup(void)
135 {
136 plat_cci_init();
137 plat_cci_enable();
138
139 plat_configure_mmu_el3(BL_CODE_BASE,
140 BL_COHERENT_RAM_END - BL_CODE_BASE,
141 BL_CODE_BASE,
142 BL_CODE_END,
143 BL_COHERENT_RAM_BASE,
144 BL_COHERENT_RAM_END);
145 }
146
147