1 /* 2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 15 #include "zynqmp_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #define PLATFORM_STACK_SIZE 0x440 23 24 #define PLATFORM_CORE_COUNT U(4) 25 #define PLAT_NUM_POWER_DOMAINS U(5) 26 #define PLAT_MAX_PWR_LVL U(1) 27 #define PLAT_MAX_RET_STATE U(1) 28 #define PLAT_MAX_OFF_STATE U(2) 29 30 /******************************************************************************* 31 * BL31 specific defines. 32 ******************************************************************************/ 33 /* 34 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 35 * present). BL31_BASE is calculated using the current BL31 debug size plus a 36 * little space for growth. 37 */ 38 #ifndef ZYNQMP_ATF_MEM_BASE 39 #if !DEBUG && defined(SPD_none) 40 # define BL31_BASE 0xfffea000 41 # define BL31_LIMIT 0xffffffff 42 #else 43 # define BL31_BASE 0x1000 44 # define BL31_LIMIT 0x7ffff 45 #endif 46 #else 47 # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 48 # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 49 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 50 # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 51 # endif 52 #endif 53 54 /******************************************************************************* 55 * BL32 specific defines. 56 ******************************************************************************/ 57 #ifndef ZYNQMP_BL32_MEM_BASE 58 # define BL32_BASE 0x60000000 59 # define BL32_LIMIT 0x7fffffff 60 #else 61 # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 62 # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 63 #endif 64 65 /******************************************************************************* 66 * BL33 specific defines. 67 ******************************************************************************/ 68 #ifndef PRELOADED_BL33_BASE 69 # define PLAT_ARM_NS_IMAGE_BASE 0x8000000 70 #else 71 # define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE 72 #endif 73 74 /******************************************************************************* 75 * TSP specific defines. 76 ******************************************************************************/ 77 #define TSP_SEC_MEM_BASE BL32_BASE 78 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 79 80 /* ID of the secure physical generic timer interrupt used by the TSP */ 81 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 82 83 /******************************************************************************* 84 * Platform specific page table and MMU setup constants 85 ******************************************************************************/ 86 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 87 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 88 #define MAX_MMAP_REGIONS 7 89 #define MAX_XLAT_TABLES 5 90 91 #define CACHE_WRITEBACK_SHIFT 6 92 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 93 94 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 95 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 96 /* 97 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 98 * terminology. On a GICv2 system or mode, the lists will be merged and treated 99 * as Group 0 interrupts. 100 */ 101 #if !ZYNQMP_WDT_RESTART 102 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 103 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 104 GIC_INTR_CFG_LEVEL), \ 105 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 106 GIC_INTR_CFG_EDGE), \ 107 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 108 GIC_INTR_CFG_EDGE), \ 109 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 110 GIC_INTR_CFG_EDGE), \ 111 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 112 GIC_INTR_CFG_EDGE), \ 113 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 114 GIC_INTR_CFG_EDGE), \ 115 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 116 GIC_INTR_CFG_EDGE), \ 117 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 118 GIC_INTR_CFG_EDGE), \ 119 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 120 GIC_INTR_CFG_EDGE) 121 #else 122 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 123 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 124 GIC_INTR_CFG_LEVEL), \ 125 INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 126 GIC_INTR_CFG_EDGE), \ 127 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 128 GIC_INTR_CFG_EDGE), \ 129 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 130 GIC_INTR_CFG_EDGE), \ 131 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 132 GIC_INTR_CFG_EDGE), \ 133 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 134 GIC_INTR_CFG_EDGE), \ 135 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 136 GIC_INTR_CFG_EDGE), \ 137 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 138 GIC_INTR_CFG_EDGE), \ 139 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 140 GIC_INTR_CFG_EDGE), \ 141 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 142 GIC_INTR_CFG_EDGE) 143 #endif 144 145 #define PLAT_ARM_G0_IRQ_PROPS(grp) 146 147 #endif /* PLATFORM_DEF_H */ 148