1 #include <stdint.h>
2
3 #if CPUINFO_MOCK
4 #include <cpuinfo-mock.h>
5 #endif
6 #include <arm/linux/api.h>
7 #include <arm/linux/cp.h>
8 #include <arm/midr.h>
9 #include <cpuinfo/log.h>
10
11
12 #if CPUINFO_MOCK
13 uint32_t cpuinfo_arm_fpsid = 0;
14 uint32_t cpuinfo_arm_mvfr0 = 0;
15 uint32_t cpuinfo_arm_wcid = 0;
16
cpuinfo_set_fpsid(uint32_t fpsid)17 void cpuinfo_set_fpsid(uint32_t fpsid) {
18 cpuinfo_arm_fpsid = fpsid;
19 }
20
cpuinfo_set_wcid(uint32_t wcid)21 void cpuinfo_set_wcid(uint32_t wcid) {
22 cpuinfo_arm_wcid = wcid;
23 }
24 #endif
25
26
cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(uint32_t features,uint32_t features2,uint32_t midr,uint32_t architecture_version,uint32_t architecture_flags,const struct cpuinfo_arm_chipset chipset[restrict static1],struct cpuinfo_arm_isa isa[restrict static1])27 void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
28 uint32_t features,
29 uint32_t features2,
30 uint32_t midr,
31 uint32_t architecture_version,
32 uint32_t architecture_flags,
33 const struct cpuinfo_arm_chipset chipset[restrict static 1],
34 struct cpuinfo_arm_isa isa[restrict static 1])
35 {
36 if (architecture_version >= 8) {
37 /*
38 * ARMv7 code running on ARMv8: IDIV, VFP, NEON are always supported,
39 * but may be not reported in /proc/cpuinfo features.
40 */
41 isa->armv5e = true;
42 isa->armv6 = true;
43 isa->armv6k = true;
44 isa->armv7 = true;
45 isa->armv7mp = true;
46 isa->armv8 = true;
47 isa->thumb = true;
48 isa->thumb2 = true;
49 isa->idiv = true;
50 isa->vfpv3 = true;
51 isa->d32 = true;
52 isa->fp16 = true;
53 isa->fma = true;
54 isa->neon = true;
55
56 /*
57 * NEON FP16 compute extension and VQRDMLAH/VQRDMLSH instructions are not indicated in /proc/cpuinfo.
58 * Use a MIDR-based heuristic to whitelist processors known to support it:
59 * - Processors with Cortex-A55 cores
60 * - Processors with Cortex-A65 cores
61 * - Processors with Cortex-A75 cores
62 * - Processors with Cortex-A76 cores
63 * - Processors with Cortex-A77 cores
64 * - Processors with Exynos M4 cores
65 * - Processors with Exynos M5 cores
66 * - Neoverse N1 cores
67 */
68 if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) {
69 /* Only little cores of Exynos 9810 support FP16 & RDM */
70 cpuinfo_log_warning("FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions");
71 } else {
72 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
73 case UINT32_C(0x4100D050): /* Cortex-A55 */
74 case UINT32_C(0x4100D060): /* Cortex-A65 */
75 case UINT32_C(0x4100D0B0): /* Cortex-A76 */
76 case UINT32_C(0x4100D0C0): /* Neoverse N1 */
77 case UINT32_C(0x4100D0D0): /* Cortex-A77 */
78 case UINT32_C(0x4100D0E0): /* Cortex-A76AE */
79 case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
80 case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */
81 case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */
82 case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */
83 case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */
84 case UINT32_C(0x53000030): /* Exynos M4 */
85 case UINT32_C(0x53000040): /* Exynos M5 */
86 isa->fp16arith = true;
87 isa->rdm = true;
88 break;
89 }
90 }
91
92 /*
93 * NEON VDOT instructions are not indicated in /proc/cpuinfo.
94 * Use a MIDR-based heuristic to whitelist processors known to support it.
95 */
96 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
97 case UINT32_C(0x4100D0B0): /* Cortex-A76 */
98 case UINT32_C(0x4100D0D0): /* Cortex-A77 */
99 case UINT32_C(0x4100D0E0): /* Cortex-A76AE */
100 case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
101 case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */
102 case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */
103 case UINT32_C(0x53000030): /* Exynos-M4 */
104 case UINT32_C(0x53000040): /* Exynos-M5 */
105 isa->dot = true;
106 break;
107 case UINT32_C(0x4100D050): /* Cortex A55: revision 1 or later only */
108 isa->dot = !!(midr_get_variant(midr) >= 1);
109 break;
110 case UINT32_C(0x4100D0A0): /* Cortex A75: revision 2 or later only */
111 isa->dot = !!(midr_get_variant(midr) >= 2);
112 break;
113 }
114 } else {
115 /* ARMv7 or lower: use feature flags to detect optional features */
116
117 /*
118 * ARM11 (ARM 1136/1156/1176/11 MPCore) processors can report v7 architecture
119 * even though they support only ARMv6 instruction set.
120 */
121 if (architecture_version == 7 && midr_is_arm11(midr)) {
122 cpuinfo_log_warning("kernel-reported architecture ARMv7 ignored due to mismatch with processor microarchitecture (ARM11)");
123 architecture_version = 6;
124 }
125
126 if (architecture_version < 7) {
127 const uint32_t armv7_features_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | CPUINFO_ARM_LINUX_FEATURE_VFPD32 |
128 CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON | CPUINFO_ARM_LINUX_FEATURE_IDIVT | CPUINFO_ARM_LINUX_FEATURE_IDIVA;
129 if (features & armv7_features_mask) {
130 architecture_version = 7;
131 }
132 }
133 if ((architecture_version >= 6) || (features & CPUINFO_ARM_LINUX_FEATURE_EDSP) || (architecture_flags & CPUINFO_ARM_LINUX_ARCH_E)) {
134 isa->armv5e = true;
135 }
136 if (architecture_version >= 6) {
137 isa->armv6 = true;
138 }
139 if (architecture_version >= 7) {
140 isa->armv6k = true;
141 isa->armv7 = true;
142
143 /*
144 * ARMv7 MP extension (PLDW instruction) is not indicated in /proc/cpuinfo.
145 * Use heuristic list of supporting processors:
146 * - Processors supporting UDIV/SDIV instructions ("idiva" + "idivt" features in /proc/cpuinfo)
147 * - Cortex-A5
148 * - Cortex-A9
149 * - Dual-Core Scorpion
150 * - Krait (supports UDIV/SDIV, but kernels may not report it in /proc/cpuinfo)
151 *
152 * TODO: check single-core Qualcomm Scorpion.
153 */
154 switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
155 case UINT32_C(0x4100C050): /* Cortex-A5 */
156 case UINT32_C(0x4100C090): /* Cortex-A9 */
157 case UINT32_C(0x510002D0): /* Scorpion (dual-core) */
158 case UINT32_C(0x510004D0): /* Krait (dual-core) */
159 case UINT32_C(0x510006F0): /* Krait (quad-core) */
160 isa->armv7mp = true;
161 break;
162 default:
163 /* In practice IDIV instruction implies ARMv7+MP ISA */
164 isa->armv7mp = (features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV;
165 break;
166 }
167 }
168
169 if (features & CPUINFO_ARM_LINUX_FEATURE_IWMMXT) {
170 const uint32_t wcid = read_wcid();
171 cpuinfo_log_debug("WCID = 0x%08"PRIx32, wcid);
172 const uint32_t coprocessor_type = (wcid >> 8) & UINT32_C(0xFF);
173 if (coprocessor_type >= 0x10) {
174 isa->wmmx = true;
175 if (coprocessor_type >= 0x20) {
176 isa->wmmx2 = true;
177 }
178 } else {
179 cpuinfo_log_warning("WMMX ISA disabled: OS reported iwmmxt feature, "
180 "but WCID coprocessor type 0x%"PRIx32" indicates no WMMX support",
181 coprocessor_type);
182 }
183 }
184
185 if ((features & CPUINFO_ARM_LINUX_FEATURE_THUMB) || (architecture_flags & CPUINFO_ARM_LINUX_ARCH_T)) {
186 isa->thumb = true;
187
188 /*
189 * There is no separate feature flag for Thumb 2.
190 * All ARMv7 processors and ARM 1156 support Thumb 2.
191 */
192 if (architecture_version >= 7 || midr_is_arm1156(midr)) {
193 isa->thumb2 = true;
194 }
195 }
196 if (features & CPUINFO_ARM_LINUX_FEATURE_THUMBEE) {
197 isa->thumbee = true;
198 }
199 if ((features & CPUINFO_ARM_LINUX_FEATURE_JAVA) || (architecture_flags & CPUINFO_ARM_LINUX_ARCH_J)) {
200 isa->jazelle = true;
201 }
202
203 /* Qualcomm Krait may have buggy kernel configuration that doesn't report IDIV */
204 if ((features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV || midr_is_krait(midr)) {
205 isa->idiv = true;
206 }
207
208 const uint32_t vfp_mask = \
209 CPUINFO_ARM_LINUX_FEATURE_VFP | CPUINFO_ARM_LINUX_FEATURE_VFPV3 | CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | \
210 CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON;
211 if (features & vfp_mask) {
212 const uint32_t vfpv3_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | \
213 CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON;
214 if ((architecture_version >= 7) || (features & vfpv3_mask)) {
215 isa->vfpv3 = true;
216
217 const uint32_t d32_mask = CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_NEON;
218 if (features & d32_mask) {
219 isa->d32 = true;
220 }
221 } else {
222 #if defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH) && (__ARM_ARCH >= 7)
223 isa->vfpv3 = true;
224 #else
225 const uint32_t fpsid = read_fpsid();
226 cpuinfo_log_debug("FPSID = 0x%08"PRIx32, fpsid);
227 const uint32_t subarchitecture = (fpsid >> 16) & UINT32_C(0x7F);
228 if (subarchitecture >= 0x01) {
229 isa->vfpv2 = true;
230 }
231 #endif
232 }
233 }
234 if (features & CPUINFO_ARM_LINUX_FEATURE_NEON) {
235 isa->neon = true;
236 }
237
238 /*
239 * There is no separate feature flag for FP16 support.
240 * VFPv4 implies VFPv3-FP16 support (and in practice, NEON-HP as well).
241 * Additionally, ARM Cortex-A9 and Qualcomm Scorpion support FP16.
242 */
243 if ((features & CPUINFO_ARM_LINUX_FEATURE_VFPV4) || midr_is_cortex_a9(midr) || midr_is_scorpion(midr)) {
244 isa->fp16 = true;
245 }
246
247 if (features & CPUINFO_ARM_LINUX_FEATURE_VFPV4) {
248 isa->fma = true;
249 }
250 }
251
252 if (features2 & CPUINFO_ARM_LINUX_FEATURE2_AES) {
253 isa->aes = true;
254 }
255 if (features2 & CPUINFO_ARM_LINUX_FEATURE2_PMULL) {
256 isa->pmull = true;
257 }
258 if (features2 & CPUINFO_ARM_LINUX_FEATURE2_SHA1) {
259 isa->sha1 = true;
260 }
261 if (features2 & CPUINFO_ARM_LINUX_FEATURE2_SHA2) {
262 isa->sha2 = true;
263 }
264 if (features2 & CPUINFO_ARM_LINUX_FEATURE2_CRC32) {
265 isa->crc32 = true;
266 }
267 }
268