1 #include <gtest/gtest.h>
2
3 #include <cpuinfo.h>
4 #include <cpuinfo-mock.h>
5
6
TEST(PROCESSORS,count)7 TEST(PROCESSORS, count) {
8 ASSERT_EQ(10, cpuinfo_get_processors_count());
9 }
10
TEST(PROCESSORS,non_null)11 TEST(PROCESSORS, non_null) {
12 ASSERT_TRUE(cpuinfo_get_processors());
13 }
14
TEST(PROCESSORS,smt_id)15 TEST(PROCESSORS, smt_id) {
16 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
18 }
19 }
20
TEST(PROCESSORS,core)21 TEST(PROCESSORS, core) {
22 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
24 }
25 }
26
TEST(PROCESSORS,cluster)27 TEST(PROCESSORS, cluster) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 switch (i) {
30 case 0:
31 case 1:
32 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
33 break;
34 case 2:
35 case 3:
36 case 4:
37 case 5:
38 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
39 break;
40 case 6:
41 case 7:
42 case 8:
43 case 9:
44 ASSERT_EQ(cpuinfo_get_cluster(2), cpuinfo_get_processor(i)->cluster);
45 break;
46 }
47 }
48 }
49
TEST(PROCESSORS,package)50 TEST(PROCESSORS, package) {
51 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
52 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
53 }
54 }
55
TEST(PROCESSORS,linux_id)56 TEST(PROCESSORS, linux_id) {
57 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
58 switch (i) {
59 case 0:
60 case 1:
61 ASSERT_EQ(i + 8, cpuinfo_get_processor(i)->linux_id);
62 break;
63 case 2:
64 case 3:
65 case 4:
66 case 5:
67 ASSERT_EQ(i + 2, cpuinfo_get_processor(i)->linux_id);
68 break;
69 case 6:
70 case 7:
71 case 8:
72 case 9:
73 ASSERT_EQ(i - 6, cpuinfo_get_processor(i)->linux_id);
74 break;
75 }
76 }
77 }
78
TEST(PROCESSORS,l1i)79 TEST(PROCESSORS, l1i) {
80 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
81 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
82 }
83 }
84
TEST(PROCESSORS,l1d)85 TEST(PROCESSORS, l1d) {
86 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
87 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
88 }
89 }
90
TEST(PROCESSORS,l2)91 TEST(PROCESSORS, l2) {
92 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
93 switch (i) {
94 case 0:
95 case 1:
96 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
97 break;
98 case 2:
99 case 3:
100 case 4:
101 case 5:
102 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
103 break;
104 case 6:
105 case 7:
106 case 8:
107 case 9:
108 ASSERT_EQ(cpuinfo_get_l2_cache(2), cpuinfo_get_processor(i)->cache.l2);
109 break;
110 }
111 }
112 }
113
TEST(PROCESSORS,l3)114 TEST(PROCESSORS, l3) {
115 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
116 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
117 }
118 }
119
TEST(PROCESSORS,l4)120 TEST(PROCESSORS, l4) {
121 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
122 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
123 }
124 }
125
TEST(CORES,count)126 TEST(CORES, count) {
127 ASSERT_EQ(10, cpuinfo_get_cores_count());
128 }
129
TEST(CORES,non_null)130 TEST(CORES, non_null) {
131 ASSERT_TRUE(cpuinfo_get_cores());
132 }
133
TEST(CORES,processor_start)134 TEST(CORES, processor_start) {
135 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
136 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
137 }
138 }
139
TEST(CORES,processor_count)140 TEST(CORES, processor_count) {
141 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
142 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
143 }
144 }
145
TEST(CORES,core_id)146 TEST(CORES, core_id) {
147 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
148 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
149 }
150 }
151
TEST(CORES,cluster)152 TEST(CORES, cluster) {
153 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
154 switch (i) {
155 case 0:
156 case 1:
157 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
158 break;
159 case 2:
160 case 3:
161 case 4:
162 case 5:
163 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
164 break;
165 case 6:
166 case 7:
167 case 8:
168 case 9:
169 ASSERT_EQ(cpuinfo_get_cluster(2), cpuinfo_get_core(i)->cluster);
170 break;
171 }
172 }
173 }
174
TEST(CORES,package)175 TEST(CORES, package) {
176 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
177 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
178 }
179 }
180
TEST(CORES,vendor)181 TEST(CORES, vendor) {
182 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
183 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
184 }
185 }
186
TEST(CORES,uarch)187 TEST(CORES, uarch) {
188 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
189 switch (i) {
190 case 0:
191 case 1:
192 ASSERT_EQ(cpuinfo_uarch_cortex_a72, cpuinfo_get_core(i)->uarch);
193 break;
194 case 2:
195 case 3:
196 case 4:
197 case 5:
198 case 6:
199 case 7:
200 case 8:
201 case 9:
202 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_core(i)->uarch);
203 break;
204 }
205 }
206 }
207
TEST(CORES,midr)208 TEST(CORES, midr) {
209 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
210 switch (i) {
211 case 0:
212 case 1:
213 ASSERT_EQ(UINT32_C(0x410FD081), cpuinfo_get_core(i)->midr);
214 break;
215 case 2:
216 case 3:
217 case 4:
218 case 5:
219 case 6:
220 case 7:
221 case 8:
222 case 9:
223 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr);
224 break;
225 }
226 }
227 }
228
TEST(CORES,DISABLED_frequency)229 TEST(CORES, DISABLED_frequency) {
230 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
231 switch (i) {
232 case 0:
233 case 1:
234 ASSERT_EQ(UINT64_C(2522000000), cpuinfo_get_core(i)->frequency);
235 break;
236 case 2:
237 case 3:
238 case 4:
239 case 5:
240 ASSERT_EQ(UINT64_C(2002000000), cpuinfo_get_core(i)->frequency);
241 break;
242 case 6:
243 case 7:
244 case 8:
245 case 9:
246 ASSERT_EQ(UINT64_C(1547000000), cpuinfo_get_core(i)->frequency);
247 break;
248 }
249 }
250 }
251
TEST(CLUSTERS,count)252 TEST(CLUSTERS, count) {
253 ASSERT_EQ(3, cpuinfo_get_clusters_count());
254 }
255
TEST(CLUSTERS,non_null)256 TEST(CLUSTERS, non_null) {
257 ASSERT_TRUE(cpuinfo_get_clusters());
258 }
259
TEST(CLUSTERS,processor_start)260 TEST(CLUSTERS, processor_start) {
261 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
262 switch (i) {
263 case 0:
264 ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start);
265 break;
266 case 1:
267 ASSERT_EQ(2, cpuinfo_get_cluster(i)->processor_start);
268 break;
269 case 2:
270 ASSERT_EQ(6, cpuinfo_get_cluster(i)->processor_start);
271 break;
272 }
273 }
274 }
275
TEST(CLUSTERS,processor_count)276 TEST(CLUSTERS, processor_count) {
277 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
278 switch (i) {
279 case 0:
280 ASSERT_EQ(2, cpuinfo_get_cluster(i)->processor_count);
281 break;
282 case 1:
283 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count);
284 break;
285 case 2:
286 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count);
287 break;
288 }
289 }
290 }
291
TEST(CLUSTERS,core_start)292 TEST(CLUSTERS, core_start) {
293 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
294 switch (i) {
295 case 0:
296 ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start);
297 break;
298 case 1:
299 ASSERT_EQ(2, cpuinfo_get_cluster(i)->core_start);
300 break;
301 case 2:
302 ASSERT_EQ(6, cpuinfo_get_cluster(i)->core_start);
303 break;
304 }
305 }
306 }
307
TEST(CLUSTERS,core_count)308 TEST(CLUSTERS, core_count) {
309 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
310 switch (i) {
311 case 0:
312 ASSERT_EQ(2, cpuinfo_get_cluster(i)->core_count);
313 break;
314 case 1:
315 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count);
316 break;
317 case 2:
318 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count);
319 break;
320 }
321 }
322 }
323
TEST(CLUSTERS,cluster_id)324 TEST(CLUSTERS, cluster_id) {
325 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
326 ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id);
327 }
328 }
329
TEST(CLUSTERS,package)330 TEST(CLUSTERS, package) {
331 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
332 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package);
333 }
334 }
335
TEST(CLUSTERS,vendor)336 TEST(CLUSTERS, vendor) {
337 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
338 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor);
339 }
340 }
341
TEST(CLUSTERS,uarch)342 TEST(CLUSTERS, uarch) {
343 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
344 switch (i) {
345 case 0:
346 ASSERT_EQ(cpuinfo_uarch_cortex_a72, cpuinfo_get_cluster(i)->uarch);
347 break;
348 case 1:
349 case 2:
350 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_cluster(i)->uarch);
351 break;
352 }
353 }
354 }
355
TEST(CLUSTERS,midr)356 TEST(CLUSTERS, midr) {
357 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
358 switch (i) {
359 case 0:
360 ASSERT_EQ(UINT32_C(0x410FD081), cpuinfo_get_cluster(i)->midr);
361 break;
362 case 1:
363 case 2:
364 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_cluster(i)->midr);
365 break;
366 }
367 }
368 }
369
TEST(CLUSTERS,DISABLED_frequency)370 TEST(CLUSTERS, DISABLED_frequency) {
371 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
372 switch (i) {
373 case 0:
374 ASSERT_EQ(UINT64_C(2522000000), cpuinfo_get_cluster(i)->frequency);
375 break;
376 case 1:
377 ASSERT_EQ(UINT64_C(2002000000), cpuinfo_get_cluster(i)->frequency);
378 break;
379 case 2:
380 ASSERT_EQ(UINT64_C(1547000000), cpuinfo_get_cluster(i)->frequency);
381 break;
382 }
383 }
384 }
385
TEST(PACKAGES,count)386 TEST(PACKAGES, count) {
387 ASSERT_EQ(1, cpuinfo_get_packages_count());
388 }
389
TEST(PACKAGES,name)390 TEST(PACKAGES, name) {
391 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
392 ASSERT_EQ("MediaTek MT6797T",
393 std::string(cpuinfo_get_package(i)->name,
394 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
395 }
396 }
397
TEST(PACKAGES,processor_start)398 TEST(PACKAGES, processor_start) {
399 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
400 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
401 }
402 }
403
TEST(PACKAGES,processor_count)404 TEST(PACKAGES, processor_count) {
405 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
406 ASSERT_EQ(10, cpuinfo_get_package(i)->processor_count);
407 }
408 }
409
TEST(PACKAGES,core_start)410 TEST(PACKAGES, core_start) {
411 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
412 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
413 }
414 }
415
TEST(PACKAGES,core_count)416 TEST(PACKAGES, core_count) {
417 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
418 ASSERT_EQ(10, cpuinfo_get_package(i)->core_count);
419 }
420 }
421
TEST(PACKAGES,cluster_start)422 TEST(PACKAGES, cluster_start) {
423 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
424 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
425 }
426 }
427
TEST(PACKAGES,cluster_count)428 TEST(PACKAGES, cluster_count) {
429 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
430 ASSERT_EQ(3, cpuinfo_get_package(i)->cluster_count);
431 }
432 }
433
TEST(ISA,thumb)434 TEST(ISA, thumb) {
435 #if CPUINFO_ARCH_ARM
436 ASSERT_TRUE(cpuinfo_has_arm_thumb());
437 #elif CPUINFO_ARCH_ARM64
438 ASSERT_FALSE(cpuinfo_has_arm_thumb());
439 #endif
440 }
441
TEST(ISA,thumb2)442 TEST(ISA, thumb2) {
443 #if CPUINFO_ARCH_ARM
444 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
445 #elif CPUINFO_ARCH_ARM64
446 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
447 #endif
448 }
449
TEST(ISA,armv5e)450 TEST(ISA, armv5e) {
451 #if CPUINFO_ARCH_ARM
452 ASSERT_TRUE(cpuinfo_has_arm_v5e());
453 #elif CPUINFO_ARCH_ARM64
454 ASSERT_FALSE(cpuinfo_has_arm_v5e());
455 #endif
456 }
457
TEST(ISA,armv6)458 TEST(ISA, armv6) {
459 #if CPUINFO_ARCH_ARM
460 ASSERT_TRUE(cpuinfo_has_arm_v6());
461 #elif CPUINFO_ARCH_ARM64
462 ASSERT_FALSE(cpuinfo_has_arm_v6());
463 #endif
464 }
465
TEST(ISA,armv6k)466 TEST(ISA, armv6k) {
467 #if CPUINFO_ARCH_ARM
468 ASSERT_TRUE(cpuinfo_has_arm_v6k());
469 #elif CPUINFO_ARCH_ARM64
470 ASSERT_FALSE(cpuinfo_has_arm_v6k());
471 #endif
472 }
473
TEST(ISA,armv7)474 TEST(ISA, armv7) {
475 #if CPUINFO_ARCH_ARM
476 ASSERT_TRUE(cpuinfo_has_arm_v7());
477 #elif CPUINFO_ARCH_ARM64
478 ASSERT_FALSE(cpuinfo_has_arm_v7());
479 #endif
480 }
481
TEST(ISA,armv7mp)482 TEST(ISA, armv7mp) {
483 #if CPUINFO_ARCH_ARM
484 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
485 #elif CPUINFO_ARCH_ARM64
486 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
487 #endif
488 }
489
TEST(ISA,idiv)490 TEST(ISA, idiv) {
491 ASSERT_TRUE(cpuinfo_has_arm_idiv());
492 }
493
TEST(ISA,vfpv2)494 TEST(ISA, vfpv2) {
495 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
496 }
497
TEST(ISA,vfpv3)498 TEST(ISA, vfpv3) {
499 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
500 }
501
TEST(ISA,vfpv3_d32)502 TEST(ISA, vfpv3_d32) {
503 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
504 }
505
TEST(ISA,vfpv3_fp16)506 TEST(ISA, vfpv3_fp16) {
507 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
508 }
509
TEST(ISA,vfpv3_fp16_d32)510 TEST(ISA, vfpv3_fp16_d32) {
511 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
512 }
513
TEST(ISA,vfpv4)514 TEST(ISA, vfpv4) {
515 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
516 }
517
TEST(ISA,vfpv4_d32)518 TEST(ISA, vfpv4_d32) {
519 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
520 }
521
TEST(ISA,wmmx)522 TEST(ISA, wmmx) {
523 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
524 }
525
TEST(ISA,wmmx2)526 TEST(ISA, wmmx2) {
527 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
528 }
529
TEST(ISA,neon)530 TEST(ISA, neon) {
531 ASSERT_TRUE(cpuinfo_has_arm_neon());
532 }
533
TEST(ISA,neon_fp16)534 TEST(ISA, neon_fp16) {
535 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
536 }
537
TEST(ISA,neon_fma)538 TEST(ISA, neon_fma) {
539 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
540 }
541
TEST(ISA,atomics)542 TEST(ISA, atomics) {
543 ASSERT_FALSE(cpuinfo_has_arm_atomics());
544 }
545
TEST(ISA,neon_rdm)546 TEST(ISA, neon_rdm) {
547 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
548 }
549
TEST(ISA,fp16_arith)550 TEST(ISA, fp16_arith) {
551 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
552 }
553
TEST(ISA,neon_fp16_arith)554 TEST(ISA, neon_fp16_arith) {
555 ASSERT_FALSE(cpuinfo_has_arm_neon_fp16_arith());
556 }
557
TEST(ISA,neon_dot)558 TEST(ISA, neon_dot) {
559 ASSERT_FALSE(cpuinfo_has_arm_neon_dot());
560 }
561
TEST(ISA,jscvt)562 TEST(ISA, jscvt) {
563 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
564 }
565
TEST(ISA,fcma)566 TEST(ISA, fcma) {
567 ASSERT_FALSE(cpuinfo_has_arm_fcma());
568 }
569
TEST(ISA,aes)570 TEST(ISA, aes) {
571 ASSERT_TRUE(cpuinfo_has_arm_aes());
572 }
573
TEST(ISA,sha1)574 TEST(ISA, sha1) {
575 ASSERT_TRUE(cpuinfo_has_arm_sha1());
576 }
577
TEST(ISA,sha2)578 TEST(ISA, sha2) {
579 ASSERT_TRUE(cpuinfo_has_arm_sha2());
580 }
581
TEST(ISA,pmull)582 TEST(ISA, pmull) {
583 ASSERT_TRUE(cpuinfo_has_arm_pmull());
584 }
585
TEST(ISA,crc32)586 TEST(ISA, crc32) {
587 ASSERT_TRUE(cpuinfo_has_arm_crc32());
588 }
589
TEST(L1I,count)590 TEST(L1I, count) {
591 ASSERT_EQ(10, cpuinfo_get_l1i_caches_count());
592 }
593
TEST(L1I,non_null)594 TEST(L1I, non_null) {
595 ASSERT_TRUE(cpuinfo_get_l1i_caches());
596 }
597
TEST(L1I,size)598 TEST(L1I, size) {
599 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
600 switch (i) {
601 case 0:
602 case 1:
603 ASSERT_EQ(48 * 1024, cpuinfo_get_l1i_cache(i)->size);
604 break;
605 case 2:
606 case 3:
607 case 4:
608 case 5:
609 case 6:
610 case 7:
611 case 8:
612 case 9:
613 ASSERT_EQ(16 * 1024, cpuinfo_get_l1i_cache(i)->size);
614 break;
615 }
616 }
617 }
618
TEST(L1I,associativity)619 TEST(L1I, associativity) {
620 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
621 switch (i) {
622 case 0:
623 case 1:
624 ASSERT_EQ(3, cpuinfo_get_l1i_cache(i)->associativity);
625 break;
626 case 2:
627 case 3:
628 case 4:
629 case 5:
630 case 6:
631 case 7:
632 case 8:
633 case 9:
634 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity);
635 break;
636 }
637 }
638 }
639
TEST(L1I,sets)640 TEST(L1I, sets) {
641 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
642 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
643 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
644 }
645 }
646
TEST(L1I,partitions)647 TEST(L1I, partitions) {
648 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
649 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
650 }
651 }
652
TEST(L1I,line_size)653 TEST(L1I, line_size) {
654 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
655 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
656 }
657 }
658
TEST(L1I,flags)659 TEST(L1I, flags) {
660 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
661 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
662 }
663 }
664
TEST(L1I,processors)665 TEST(L1I, processors) {
666 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
667 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
668 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
669 }
670 }
671
TEST(L1D,count)672 TEST(L1D, count) {
673 ASSERT_EQ(10, cpuinfo_get_l1d_caches_count());
674 }
675
TEST(L1D,non_null)676 TEST(L1D, non_null) {
677 ASSERT_TRUE(cpuinfo_get_l1d_caches());
678 }
679
TEST(L1D,size)680 TEST(L1D, size) {
681 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
682 switch (i) {
683 case 0:
684 case 1:
685 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
686 break;
687 case 2:
688 case 3:
689 case 4:
690 case 5:
691 case 6:
692 case 7:
693 case 8:
694 case 9:
695 ASSERT_EQ(16 * 1024, cpuinfo_get_l1d_cache(i)->size);
696 break;
697 }
698 }
699 }
700
TEST(L1D,associativity)701 TEST(L1D, associativity) {
702 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
703 switch (i) {
704 case 0:
705 case 1:
706 ASSERT_EQ(2, cpuinfo_get_l1d_cache(i)->associativity);
707 break;
708 case 2:
709 case 3:
710 case 4:
711 case 5:
712 case 6:
713 case 7:
714 case 8:
715 case 9:
716 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
717 break;
718 }
719 }
720 }
721
TEST(L1D,sets)722 TEST(L1D, sets) {
723 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
724 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
725 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
726 }
727 }
728
TEST(L1D,partitions)729 TEST(L1D, partitions) {
730 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
731 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
732 }
733 }
734
TEST(L1D,line_size)735 TEST(L1D, line_size) {
736 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
737 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
738 }
739 }
740
TEST(L1D,flags)741 TEST(L1D, flags) {
742 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
743 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
744 }
745 }
746
TEST(L1D,processors)747 TEST(L1D, processors) {
748 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
749 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
750 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
751 }
752 }
753
TEST(L2,count)754 TEST(L2, count) {
755 ASSERT_EQ(3, cpuinfo_get_l2_caches_count());
756 }
757
TEST(L2,non_null)758 TEST(L2, non_null) {
759 ASSERT_TRUE(cpuinfo_get_l2_caches());
760 }
761
TEST(L2,size)762 TEST(L2, size) {
763 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
764 switch (i) {
765 case 0:
766 ASSERT_EQ(1 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size);
767 break;
768 case 1:
769 case 2:
770 ASSERT_EQ(256 * 1024, cpuinfo_get_l2_cache(i)->size);
771 break;
772 }
773 }
774 }
775
TEST(L2,associativity)776 TEST(L2, associativity) {
777 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
778 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
779 }
780 }
781
TEST(L2,sets)782 TEST(L2, sets) {
783 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
784 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
785 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
786 }
787 }
788
TEST(L2,partitions)789 TEST(L2, partitions) {
790 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
791 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
792 }
793 }
794
TEST(L2,line_size)795 TEST(L2, line_size) {
796 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
797 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
798 }
799 }
800
TEST(L2,flags)801 TEST(L2, flags) {
802 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
803 switch (i) {
804 case 0:
805 ASSERT_EQ(CPUINFO_CACHE_INCLUSIVE, cpuinfo_get_l2_cache(i)->flags);
806 break;
807 case 1:
808 case 2:
809 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
810 break;
811 }
812 }
813 }
814
TEST(L2,processors)815 TEST(L2, processors) {
816 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
817 switch (i) {
818 case 0:
819 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
820 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_count);
821 break;
822 case 1:
823 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_start);
824 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
825 break;
826 case 2:
827 ASSERT_EQ(6, cpuinfo_get_l2_cache(i)->processor_start);
828 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
829 break;
830 }
831 }
832 }
833
TEST(L3,none)834 TEST(L3, none) {
835 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
836 ASSERT_FALSE(cpuinfo_get_l3_caches());
837 }
838
TEST(L4,none)839 TEST(L4, none) {
840 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
841 ASSERT_FALSE(cpuinfo_get_l4_caches());
842 }
843
844 #include <meizu-pro-6s.h>
845
main(int argc,char * argv[])846 int main(int argc, char* argv[]) {
847 #if CPUINFO_ARCH_ARM
848 cpuinfo_set_hwcap(UINT32_C(0x0037B0D6));
849 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
850 #elif CPUINFO_ARCH_ARM64
851 cpuinfo_set_hwcap(UINT32_C(0x000000FF));
852 #endif
853 cpuinfo_mock_filesystem(filesystem);
854 #ifdef __ANDROID__
855 cpuinfo_mock_android_properties(properties);
856 #endif
857 cpuinfo_initialize();
858 ::testing::InitGoogleTest(&argc, argv);
859 return RUN_ALL_TESTS();
860 }