1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Jesse Barnes <jbarnes@virtuousgeek.org> (based on gem_bad_blit.c)
26 *
27 */
28
29 #include "igt.h"
30 #include <stdlib.h>
31 #include <stdio.h>
32 #include <string.h>
33 #include <fcntl.h>
34 #include <inttypes.h>
35 #include <errno.h>
36 #include <sys/stat.h>
37 #include <sys/time.h>
38 #include "drm.h"
39
40 IGT_TEST_DESCRIPTION("Basic CS check using MI_STORE_DATA_IMM.");
41
42 #define LOCAL_I915_EXEC_VEBOX (4<<0)
43
44 static int devid;
45
46 /*
47 * Testcase: Basic bsd MI check using MI_STORE_DATA_IMM
48 */
49
50 static unsigned coherent_domain;
51
52 static void *
mmap_coherent(int fd,uint32_t handle,int size)53 mmap_coherent(int fd, uint32_t handle, int size)
54 {
55 if (gem_has_llc(fd)) {
56 coherent_domain = I915_GEM_DOMAIN_CPU;
57 return gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
58 } else if (gem_mmap__has_wc(fd)) {
59 coherent_domain = I915_GEM_DOMAIN_WC;
60 return gem_mmap__wc(fd, handle, 0, size, PROT_WRITE);
61 } else {
62 coherent_domain = I915_GEM_DOMAIN_GTT;
63 return gem_mmap__gtt(fd, handle, size, PROT_WRITE);
64 }
65 }
66
67 static void
store_dword_loop(int fd,int ring,int divider)68 store_dword_loop(int fd, int ring, int divider)
69 {
70 int i, val = 0;
71 struct drm_i915_gem_execbuffer2 execbuf;
72 struct drm_i915_gem_exec_object2 obj[2];
73 struct drm_i915_gem_relocation_entry reloc[divider];
74 uint32_t handle[divider];
75 uint32_t *batch[divider];
76 uint32_t *target;
77 int gen = intel_gen(devid);
78
79 memset(obj, 0, sizeof(obj));
80 obj[0].handle = gem_create(fd, 4096);
81 target = mmap_coherent(fd, obj[0].handle, 4096);
82
83 memset(reloc, 0, sizeof(reloc));
84 for (i = 0; i < divider; i++) {
85 uint32_t *b;
86
87 handle[i] = gem_create(fd, 4096);
88 batch[i] = mmap_coherent(fd, handle[i], 4096);
89 gem_set_domain(fd, handle[i], coherent_domain, coherent_domain);
90
91 b = batch[i];
92 *b++ = MI_STORE_DWORD_IMM;
93 *b++ = 0;
94 *b++ = 0;
95 *b++ = 0;
96 *b++ = MI_BATCH_BUFFER_END;
97
98 reloc[i].target_handle = obj[0].handle;
99 reloc[i].offset = 4;
100 if (gen < 8)
101 reloc[i].offset += 4;
102 reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
103 reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
104 obj[1].relocation_count = 1;
105 }
106
107 memset(&execbuf, 0, sizeof(execbuf));
108 execbuf.buffers_ptr = to_user_pointer(obj);
109 execbuf.buffer_count = 2;
110 execbuf.flags = ring;
111
112 igt_info("running storedw loop on render with stall every %i batch\n", divider);
113
114 for (i = 0; i < SLOW_QUICK(0x2000, 0x10); i++) {
115 int j = i % divider;
116
117 gem_set_domain(fd, handle[j], coherent_domain, coherent_domain);
118 batch[j][3] = val;
119 obj[1].handle = handle[j];
120 obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
121 gem_execbuf(fd, &execbuf);
122
123 if (j == 0) {
124 gem_set_domain(fd, obj[0].handle, coherent_domain, 0);
125 igt_assert_f(*target == val,
126 "%d: value mismatch: stored 0x%08x, expected 0x%08x\n",
127 i, *target, val);
128 }
129
130 val++;
131 }
132
133 gem_set_domain(fd, obj[0].handle, coherent_domain, 0);
134 igt_info("completed %d writes successfully, current value: 0x%08x\n",
135 i, target[0]);
136
137 munmap(target, 4096);
138 gem_close(fd, obj[0].handle);
139 for (i = 0; i < divider; ++i) {
140 munmap(batch[i], 4096);
141 gem_close(fd, handle[i]);
142 }
143 }
144
145 static void
store_test(int fd,int ring)146 store_test(int fd, int ring)
147 {
148 gem_require_ring(fd, ring);
149 store_dword_loop(fd, ring, 1);
150 store_dword_loop(fd, ring, 2);
151 if (!igt_run_in_simulation()) {
152 store_dword_loop(fd, ring, 3);
153 store_dword_loop(fd, ring, 5);
154 store_dword_loop(fd, ring, 7);
155 store_dword_loop(fd, ring, 11);
156 store_dword_loop(fd, ring, 13);
157 store_dword_loop(fd, ring, 17);
158 store_dword_loop(fd, ring, 19);
159 }
160 }
161
162 static void
check_test_requirements(int fd,int ringid)163 check_test_requirements(int fd, int ringid)
164 {
165 gem_require_ring(fd, ringid);
166 igt_require(gem_can_store_dword(fd, ringid));
167 }
168
169 igt_main
170 {
171 const struct intel_execution_engine *e;
172 int fd;
173
174 igt_fixture {
175 fd = drm_open_driver(DRIVER_INTEL);
176 devid = intel_get_drm_devid(fd);
177
178 igt_skip_on_f(intel_gen(devid) < 6,
179 "MI_STORE_DATA can only use GTT address on gen4+/g33 and "
180 "needs snoopable mem on pre-gen6\n");
181
182 /* This only works with ppgtt */
183 igt_require(gem_uses_ppgtt(fd));
184 }
185
186 for (e = intel_execution_engines; e->name; e++) {
187 igt_subtest_f("store-%s", e->name) {
188 check_test_requirements(fd, e->exec_id);
189 store_test(fd, e->exec_id | e->flags);
190 }
191 }
192
193 igt_fixture {
194 close(fd);
195 }
196 }
197