1 //===--- PPC.cpp - Implement PPC target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements PPC TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "PPC.h"
14 #include "clang/Basic/Diagnostic.h"
15 #include "clang/Basic/MacroBuilder.h"
16 #include "clang/Basic/TargetBuiltins.h"
17
18 using namespace clang;
19 using namespace clang::targets;
20
21 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
22 #define BUILTIN(ID, TYPE, ATTRS) \
23 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
24 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
25 {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
26 #include "clang/Basic/BuiltinsPPC.def"
27 };
28
29 /// handleTargetFeatures - Perform initialization based on the user
30 /// configured set of features.
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)31 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
32 DiagnosticsEngine &Diags) {
33 FloatABI = HardFloat;
34 for (const auto &Feature : Features) {
35 if (Feature == "+altivec") {
36 HasAltivec = true;
37 } else if (Feature == "+vsx") {
38 HasVSX = true;
39 } else if (Feature == "+bpermd") {
40 HasBPERMD = true;
41 } else if (Feature == "+extdiv") {
42 HasExtDiv = true;
43 } else if (Feature == "+power8-vector") {
44 HasP8Vector = true;
45 } else if (Feature == "+crypto") {
46 HasP8Crypto = true;
47 } else if (Feature == "+direct-move") {
48 HasDirectMove = true;
49 } else if (Feature == "+htm") {
50 HasHTM = true;
51 } else if (Feature == "+float128") {
52 HasFloat128 = true;
53 } else if (Feature == "+power9-vector") {
54 HasP9Vector = true;
55 } else if (Feature == "+power10-vector") {
56 HasP10Vector = true;
57 } else if (Feature == "+pcrelative-memops") {
58 HasPCRelativeMemops = true;
59 } else if (Feature == "+spe") {
60 HasSPE = true;
61 LongDoubleWidth = LongDoubleAlign = 64;
62 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
63 } else if (Feature == "-hard-float") {
64 FloatABI = SoftFloat;
65 } else if (Feature == "+paired-vector-memops") {
66 PairedVectorMemops = true;
67 } else if (Feature == "+mma") {
68 HasMMA = true;
69 }
70 // TODO: Finish this list and add an assert that we've handled them
71 // all.
72 }
73
74 return true;
75 }
76
77 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
78 /// #defines that are not tied to a specific subtarget.
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const79 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
80 MacroBuilder &Builder) const {
81 // Target identification.
82 Builder.defineMacro("__ppc__");
83 Builder.defineMacro("__PPC__");
84 Builder.defineMacro("_ARCH_PPC");
85 Builder.defineMacro("__powerpc__");
86 Builder.defineMacro("__POWERPC__");
87 if (PointerWidth == 64) {
88 Builder.defineMacro("_ARCH_PPC64");
89 Builder.defineMacro("__powerpc64__");
90 Builder.defineMacro("__ppc64__");
91 Builder.defineMacro("__PPC64__");
92 }
93
94 // Target properties.
95 if (getTriple().getArch() == llvm::Triple::ppc64le) {
96 Builder.defineMacro("_LITTLE_ENDIAN");
97 } else {
98 if (!getTriple().isOSNetBSD() &&
99 !getTriple().isOSOpenBSD())
100 Builder.defineMacro("_BIG_ENDIAN");
101 }
102
103 // ABI options.
104 if (ABI == "elfv1")
105 Builder.defineMacro("_CALL_ELF", "1");
106 if (ABI == "elfv2")
107 Builder.defineMacro("_CALL_ELF", "2");
108
109 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
110 // our support post-dates this and it should work on all 64-bit ppc linux
111 // platforms. It is guaranteed to work on all elfv2 platforms.
112 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64)
113 Builder.defineMacro("_CALL_LINUX", "1");
114
115 // Subtarget options.
116 if (!getTriple().isOSAIX()){
117 Builder.defineMacro("__NATURAL_ALIGNMENT__");
118 }
119 Builder.defineMacro("__REGISTER_PREFIX__", "");
120
121 // FIXME: Should be controlled by command line option.
122 if (LongDoubleWidth == 128) {
123 Builder.defineMacro("__LONG_DOUBLE_128__");
124 Builder.defineMacro("__LONGDOUBLE128");
125 if (Opts.PPCIEEELongDouble)
126 Builder.defineMacro("__LONG_DOUBLE_IEEE128__");
127 else
128 Builder.defineMacro("__LONG_DOUBLE_IBM128__");
129 }
130
131 // Define this for elfv2 (64-bit only) or 64-bit darwin.
132 if (ABI == "elfv2" ||
133 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64))
134 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
135
136 if (ArchDefs & ArchDefineName)
137 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
138 if (ArchDefs & ArchDefinePpcgr)
139 Builder.defineMacro("_ARCH_PPCGR");
140 if (ArchDefs & ArchDefinePpcsq)
141 Builder.defineMacro("_ARCH_PPCSQ");
142 if (ArchDefs & ArchDefine440)
143 Builder.defineMacro("_ARCH_440");
144 if (ArchDefs & ArchDefine603)
145 Builder.defineMacro("_ARCH_603");
146 if (ArchDefs & ArchDefine604)
147 Builder.defineMacro("_ARCH_604");
148 if (ArchDefs & ArchDefinePwr4)
149 Builder.defineMacro("_ARCH_PWR4");
150 if (ArchDefs & ArchDefinePwr5)
151 Builder.defineMacro("_ARCH_PWR5");
152 if (ArchDefs & ArchDefinePwr5x)
153 Builder.defineMacro("_ARCH_PWR5X");
154 if (ArchDefs & ArchDefinePwr6)
155 Builder.defineMacro("_ARCH_PWR6");
156 if (ArchDefs & ArchDefinePwr6x)
157 Builder.defineMacro("_ARCH_PWR6X");
158 if (ArchDefs & ArchDefinePwr7)
159 Builder.defineMacro("_ARCH_PWR7");
160 if (ArchDefs & ArchDefinePwr8)
161 Builder.defineMacro("_ARCH_PWR8");
162 if (ArchDefs & ArchDefinePwr9)
163 Builder.defineMacro("_ARCH_PWR9");
164 if (ArchDefs & ArchDefinePwr10)
165 Builder.defineMacro("_ARCH_PWR10");
166 if (ArchDefs & ArchDefineA2)
167 Builder.defineMacro("_ARCH_A2");
168 if (ArchDefs & ArchDefineE500)
169 Builder.defineMacro("__NO_LWSYNC__");
170 if (ArchDefs & ArchDefineFuture)
171 Builder.defineMacro("_ARCH_PWR_FUTURE");
172
173 if (HasAltivec) {
174 Builder.defineMacro("__VEC__", "10206");
175 Builder.defineMacro("__ALTIVEC__");
176 }
177 if (HasSPE) {
178 Builder.defineMacro("__SPE__");
179 Builder.defineMacro("__NO_FPRS__");
180 }
181 if (HasVSX)
182 Builder.defineMacro("__VSX__");
183 if (HasP8Vector)
184 Builder.defineMacro("__POWER8_VECTOR__");
185 if (HasP8Crypto)
186 Builder.defineMacro("__CRYPTO__");
187 if (HasHTM)
188 Builder.defineMacro("__HTM__");
189 if (HasFloat128)
190 Builder.defineMacro("__FLOAT128__");
191 if (HasP9Vector)
192 Builder.defineMacro("__POWER9_VECTOR__");
193 if (HasMMA)
194 Builder.defineMacro("__MMA__");
195 if (HasP10Vector)
196 Builder.defineMacro("__POWER10_VECTOR__");
197
198 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
199 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
200 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
201 if (PointerWidth == 64)
202 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
203
204 // We have support for the bswap intrinsics so we can define this.
205 Builder.defineMacro("__HAVE_BSWAP__", "1");
206
207 // FIXME: The following are not yet generated here by Clang, but are
208 // generated by GCC:
209 //
210 // _SOFT_FLOAT_
211 // __RECIP_PRECISION__
212 // __APPLE_ALTIVEC__
213 // __RECIP__
214 // __RECIPF__
215 // __RSQRTE__
216 // __RSQRTEF__
217 // _SOFT_DOUBLE_
218 // __NO_LWSYNC__
219 // __CMODEL_MEDIUM__
220 // __CMODEL_LARGE__
221 // _CALL_SYSV
222 // _CALL_DARWIN
223 }
224
225 // Handle explicit options being passed to the compiler here: if we've
226 // explicitly turned off vsx and turned on any of:
227 // - power8-vector
228 // - direct-move
229 // - float128
230 // - power9-vector
231 // - paired-vector-memops
232 // - mma
233 // - power10-vector
234 // then go ahead and error since the customer has expressed an incompatible
235 // set of options.
ppcUserFeaturesCheck(DiagnosticsEngine & Diags,const std::vector<std::string> & FeaturesVec)236 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
237 const std::vector<std::string> &FeaturesVec) {
238
239 // vsx was not explicitly turned off.
240 if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
241 return true;
242
243 auto FindVSXSubfeature = [&](StringRef Feature, StringRef Option) {
244 if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
245 Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
246 return true;
247 }
248 return false;
249 };
250
251 bool Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector");
252 Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
253 Found |= FindVSXSubfeature("+float128", "-mfloat128");
254 Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
255 Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops");
256 Found |= FindVSXSubfeature("+mma", "-mmma");
257 Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
258
259 // Return false if any vsx subfeatures was found.
260 return !Found;
261 }
262
initFeatureMap(llvm::StringMap<bool> & Features,DiagnosticsEngine & Diags,StringRef CPU,const std::vector<std::string> & FeaturesVec) const263 bool PPCTargetInfo::initFeatureMap(
264 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
265 const std::vector<std::string> &FeaturesVec) const {
266 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
267 .Case("7400", true)
268 .Case("g4", true)
269 .Case("7450", true)
270 .Case("g4+", true)
271 .Case("970", true)
272 .Case("g5", true)
273 .Case("pwr6", true)
274 .Case("pwr7", true)
275 .Case("pwr8", true)
276 .Case("pwr9", true)
277 .Case("ppc64", true)
278 .Case("ppc64le", true)
279 .Default(false);
280
281 Features["power9-vector"] = (CPU == "pwr9");
282 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
283 .Case("ppc64le", true)
284 .Case("pwr9", true)
285 .Case("pwr8", true)
286 .Default(false);
287 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
288 .Case("ppc64le", true)
289 .Case("pwr9", true)
290 .Case("pwr8", true)
291 .Default(false);
292 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
293 .Case("ppc64le", true)
294 .Case("pwr9", true)
295 .Case("pwr8", true)
296 .Case("pwr7", true)
297 .Default(false);
298 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
299 .Case("ppc64le", true)
300 .Case("pwr9", true)
301 .Case("pwr8", true)
302 .Case("pwr7", true)
303 .Default(false);
304 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
305 .Case("ppc64le", true)
306 .Case("pwr9", true)
307 .Case("pwr8", true)
308 .Default(false);
309 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
310 .Case("ppc64le", true)
311 .Case("pwr9", true)
312 .Case("pwr8", true)
313 .Case("pwr7", true)
314 .Default(false);
315 Features["htm"] = llvm::StringSwitch<bool>(CPU)
316 .Case("ppc64le", true)
317 .Case("pwr9", true)
318 .Case("pwr8", true)
319 .Default(false);
320 Features["float128"] = llvm::StringSwitch<bool>(CPU)
321 .Case("pwr9", true)
322 .Default(false);
323
324 Features["spe"] = llvm::StringSwitch<bool>(CPU)
325 .Case("8548", true)
326 .Case("e500", true)
327 .Default(false);
328
329 // Power10 includes all the same features as Power9 plus any features specific
330 // to the Power10 core.
331 if (CPU == "pwr10" || CPU == "power10") {
332 initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
333 addP10SpecificFeatures(Features);
334 }
335
336 // Future CPU should include all of the features of Power 10 as well as any
337 // additional features (yet to be determined) specific to it.
338 if (CPU == "future") {
339 initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
340 addFutureSpecificFeatures(Features);
341 }
342
343 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
344 return false;
345
346 if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
347 llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
348 // We have __float128 on PPC but not power 9 and above.
349 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
350 return false;
351 }
352
353 if (!(ArchDefs & ArchDefinePwr10) &&
354 llvm::find(FeaturesVec, "+mma") != FeaturesVec.end()) {
355 // We have MMA on PPC but not power 10 and above.
356 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
357 return false;
358 }
359
360 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
361 }
362
363 // Add any Power10 specific features.
addP10SpecificFeatures(llvm::StringMap<bool> & Features) const364 void PPCTargetInfo::addP10SpecificFeatures(
365 llvm::StringMap<bool> &Features) const {
366 Features["htm"] = false; // HTM was removed for P10.
367 Features["paired-vector-memops"] = true;
368 Features["mma"] = true;
369 Features["power10-vector"] = true;
370 Features["pcrelative-memops"] = true;
371 return;
372 }
373
374 // Add features specific to the "Future" CPU.
addFutureSpecificFeatures(llvm::StringMap<bool> & Features) const375 void PPCTargetInfo::addFutureSpecificFeatures(
376 llvm::StringMap<bool> &Features) const {
377 return;
378 }
379
hasFeature(StringRef Feature) const380 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
381 return llvm::StringSwitch<bool>(Feature)
382 .Case("powerpc", true)
383 .Case("altivec", HasAltivec)
384 .Case("vsx", HasVSX)
385 .Case("power8-vector", HasP8Vector)
386 .Case("crypto", HasP8Crypto)
387 .Case("direct-move", HasDirectMove)
388 .Case("htm", HasHTM)
389 .Case("bpermd", HasBPERMD)
390 .Case("extdiv", HasExtDiv)
391 .Case("float128", HasFloat128)
392 .Case("power9-vector", HasP9Vector)
393 .Case("paired-vector-memops", PairedVectorMemops)
394 .Case("power10-vector", HasP10Vector)
395 .Case("pcrelative-memops", HasPCRelativeMemops)
396 .Case("spe", HasSPE)
397 .Case("mma", HasMMA)
398 .Default(false);
399 }
400
setFeatureEnabled(llvm::StringMap<bool> & Features,StringRef Name,bool Enabled) const401 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
402 StringRef Name, bool Enabled) const {
403 if (Enabled) {
404 // If we're enabling any of the vsx based features then enable vsx and
405 // altivec. We'll diagnose any problems later.
406 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
407 .Case("vsx", true)
408 .Case("direct-move", true)
409 .Case("power8-vector", true)
410 .Case("power9-vector", true)
411 .Case("paired-vector-memops", true)
412 .Case("power10-vector", true)
413 .Case("float128", true)
414 .Case("mma", true)
415 .Default(false);
416 if (FeatureHasVSX)
417 Features["vsx"] = Features["altivec"] = true;
418 if (Name == "power9-vector")
419 Features["power8-vector"] = true;
420 else if (Name == "power10-vector")
421 Features["power8-vector"] = Features["power9-vector"] = true;
422 if (Name == "pcrel")
423 Features["pcrelative-memops"] = true;
424 else
425 Features[Name] = true;
426 } else {
427 // If we're disabling altivec or vsx go ahead and disable all of the vsx
428 // features.
429 if ((Name == "altivec") || (Name == "vsx"))
430 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
431 Features["float128"] = Features["power9-vector"] =
432 Features["paired-vector-memops"] = Features["mma"] =
433 Features["power10-vector"] = false;
434 if (Name == "power8-vector")
435 Features["power9-vector"] = Features["paired-vector-memops"] =
436 Features["mma"] = Features["power10-vector"] = false;
437 else if (Name == "power9-vector")
438 Features["paired-vector-memops"] = Features["mma"] =
439 Features["power10-vector"] = false;
440 if (Name == "pcrel")
441 Features["pcrelative-memops"] = false;
442 else
443 Features[Name] = false;
444 }
445 }
446
447 const char *const PPCTargetInfo::GCCRegNames[] = {
448 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
449 "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17",
450 "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26",
451 "r27", "r28", "r29", "r30", "r31", "f0", "f1", "f2", "f3",
452 "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12",
453 "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
454 "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
455 "f31", "mq", "lr", "ctr", "ap", "cr0", "cr1", "cr2", "cr3",
456 "cr4", "cr5", "cr6", "cr7", "xer", "v0", "v1", "v2", "v3",
457 "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12",
458 "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
459 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30",
460 "v31", "vrsave", "vscr", "spe_acc", "spefscr", "sfp"
461 };
462
getGCCRegNames() const463 ArrayRef<const char *> PPCTargetInfo::getGCCRegNames() const {
464 return llvm::makeArrayRef(GCCRegNames);
465 }
466
467 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
468 // While some of these aliases do map to different registers
469 // they still share the same register name.
470 {{"0"}, "r0"}, {{"1"}, "r1"}, {{"2"}, "r2"}, {{"3"}, "r3"},
471 {{"4"}, "r4"}, {{"5"}, "r5"}, {{"6"}, "r6"}, {{"7"}, "r7"},
472 {{"8"}, "r8"}, {{"9"}, "r9"}, {{"10"}, "r10"}, {{"11"}, "r11"},
473 {{"12"}, "r12"}, {{"13"}, "r13"}, {{"14"}, "r14"}, {{"15"}, "r15"},
474 {{"16"}, "r16"}, {{"17"}, "r17"}, {{"18"}, "r18"}, {{"19"}, "r19"},
475 {{"20"}, "r20"}, {{"21"}, "r21"}, {{"22"}, "r22"}, {{"23"}, "r23"},
476 {{"24"}, "r24"}, {{"25"}, "r25"}, {{"26"}, "r26"}, {{"27"}, "r27"},
477 {{"28"}, "r28"}, {{"29"}, "r29"}, {{"30"}, "r30"}, {{"31"}, "r31"},
478 {{"fr0"}, "f0"}, {{"fr1"}, "f1"}, {{"fr2"}, "f2"}, {{"fr3"}, "f3"},
479 {{"fr4"}, "f4"}, {{"fr5"}, "f5"}, {{"fr6"}, "f6"}, {{"fr7"}, "f7"},
480 {{"fr8"}, "f8"}, {{"fr9"}, "f9"}, {{"fr10"}, "f10"}, {{"fr11"}, "f11"},
481 {{"fr12"}, "f12"}, {{"fr13"}, "f13"}, {{"fr14"}, "f14"}, {{"fr15"}, "f15"},
482 {{"fr16"}, "f16"}, {{"fr17"}, "f17"}, {{"fr18"}, "f18"}, {{"fr19"}, "f19"},
483 {{"fr20"}, "f20"}, {{"fr21"}, "f21"}, {{"fr22"}, "f22"}, {{"fr23"}, "f23"},
484 {{"fr24"}, "f24"}, {{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"},
485 {{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"}, {{"fr31"}, "f31"},
486 {{"cc"}, "cr0"},
487 };
488
getGCCRegAliases() const489 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
490 return llvm::makeArrayRef(GCCRegAliases);
491 }
492
493 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
494 // vs0 ~ vs31 is mapping to 32 - 63,
495 // vs32 ~ vs63 is mapping to 77 - 108.
496 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
497 // Table of additional register names to use in user input.
498 {{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
499 {{"vs4"}, 36}, {{"vs5"}, 37}, {{"vs6"}, 38}, {{"vs7"}, 39},
500 {{"vs8"}, 40}, {{"vs9"}, 41}, {{"vs10"}, 42}, {{"vs11"}, 43},
501 {{"vs12"}, 44}, {{"vs13"}, 45}, {{"vs14"}, 46}, {{"vs15"}, 47},
502 {{"vs16"}, 48}, {{"vs17"}, 49}, {{"vs18"}, 50}, {{"vs19"}, 51},
503 {{"vs20"}, 52}, {{"vs21"}, 53}, {{"vs22"}, 54}, {{"vs23"}, 55},
504 {{"vs24"}, 56}, {{"vs25"}, 57}, {{"vs26"}, 58}, {{"vs27"}, 59},
505 {{"vs28"}, 60}, {{"vs29"}, 61}, {{"vs30"}, 62}, {{"vs31"}, 63},
506 {{"vs32"}, 77}, {{"vs33"}, 78}, {{"vs34"}, 79}, {{"vs35"}, 80},
507 {{"vs36"}, 81}, {{"vs37"}, 82}, {{"vs38"}, 83}, {{"vs39"}, 84},
508 {{"vs40"}, 85}, {{"vs41"}, 86}, {{"vs42"}, 87}, {{"vs43"}, 88},
509 {{"vs44"}, 89}, {{"vs45"}, 90}, {{"vs46"}, 91}, {{"vs47"}, 92},
510 {{"vs48"}, 93}, {{"vs49"}, 94}, {{"vs50"}, 95}, {{"vs51"}, 96},
511 {{"vs52"}, 97}, {{"vs53"}, 98}, {{"vs54"}, 99}, {{"vs55"}, 100},
512 {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104},
513 {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108},
514 };
515
getGCCAddlRegNames() const516 ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
517 if (ABI == "elfv2")
518 return llvm::makeArrayRef(GCCAddlRegNames);
519 else
520 return TargetInfo::getGCCAddlRegNames();
521 }
522
523 static constexpr llvm::StringLiteral ValidCPUNames[] = {
524 {"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
525 {"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
526 {"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
527 {"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"},
528 {"g5"}, {"a2"}, {"e500"}, {"e500mc"}, {"e5500"},
529 {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"}, {"power5"},
530 {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"},
531 {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"},
532 {"pwr8"}, {"power9"}, {"pwr9"}, {"power10"}, {"pwr10"},
533 {"powerpc"}, {"ppc"}, {"powerpc64"}, {"ppc64"}, {"powerpc64le"},
534 {"ppc64le"}, {"future"}};
535
isValidCPUName(StringRef Name) const536 bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
537 return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);
538 }
539
fillValidCPUList(SmallVectorImpl<StringRef> & Values) const540 void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
541 Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
542 }
543
adjust(LangOptions & Opts)544 void PPCTargetInfo::adjust(LangOptions &Opts) {
545 if (HasAltivec)
546 Opts.AltiVec = 1;
547 TargetInfo::adjust(Opts);
548 if (LongDoubleFormat != &llvm::APFloat::IEEEdouble())
549 LongDoubleFormat = Opts.PPCIEEELongDouble
550 ? &llvm::APFloat::IEEEquad()
551 : &llvm::APFloat::PPCDoubleDouble();
552 }
553
getTargetBuiltins() const554 ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const {
555 return llvm::makeArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin -
556 Builtin::FirstTSBuiltin);
557 }
558