1 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=128 | FileCheck %s -D#VBITS=128 --check-prefixes=CHECK,CHECK128
2 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=256 | FileCheck %s -D#VBITS=256 --check-prefixes=CHECK,CHECKWIDE
3 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=512 | FileCheck %s -D#VBITS=512 --check-prefixes=CHECK,CHECKWIDE
4 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=1024 | FileCheck %s -D#VBITS=1024 --check-prefixes=CHECK,CHECKWIDE
5 // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=2048 | FileCheck %s -D#VBITS=2048 --check-prefixes=CHECK,CHECKWIDE
6 // REQUIRES: aarch64-registered-target
7
8 // Examples taken from section "3.7.3.3 Behavior specific to SVE
9 // vectors" of the SVE ACLE (Version 00bet6) that can be found at
10 // https://developer.arm.com/documentation/100987/latest
11 //
12 // Example has been expanded to work with mutiple values of
13 // -msve-vector-bits.
14
15 #include <arm_sve.h>
16
17 // Page 26, first paragraph of 3.7.3.3: sizeof and alignof
18 #if __ARM_FEATURE_SVE_BITS
19 #define N __ARM_FEATURE_SVE_BITS
20 typedef svfloat32_t fixed_svfloat __attribute__((arm_sve_vector_bits(N)));
test01()21 void test01() {
22 static_assert(alignof(fixed_svfloat) == 16,
23 "Invalid align of Vector Length Specific Type.");
24 static_assert(sizeof(fixed_svfloat) == N / 8,
25 "Invalid size of Vector Length Specific Type.");
26 }
27 #endif
28
29 // Page 26, items 1 and 2 of 3.7.3.3: how VLST and GNUT are related.
30 #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
31 #define N __ARM_FEATURE_SVE_BITS
32 typedef svfloat64_t fixed_svfloat64 __attribute__((arm_sve_vector_bits(N)));
33 typedef float64_t gnufloat64 __attribute__((vector_size(N / 8)));
test02()34 void test02() {
35 static_assert(alignof(fixed_svfloat64) == alignof(gnufloat64),
36 "Align of Vector Length Specific Type and GNU Vector Types "
37 "should be the same.");
38 static_assert(sizeof(fixed_svfloat64) == sizeof(gnufloat64),
39 "Size of Vector Length Specific Type and GNU Vector Types "
40 "should be the same.");
41 }
42 #endif
43
44 // Page 27, item 1.
45 #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
46 #define N __ARM_FEATURE_SVE_BITS
47 // CHECK-LABEL: define <vscale x 4 x i32> @_Z1f9__SVE_VLSIu11__SVInt32_tLj
48 // CHECK-SAME: [[#VBITS]]
49 // CHECK-SAME: EES_(<vscale x 4 x i32> %x.coerce, <vscale x 4 x i32> %y.coerce)
50 // CHECK-NEXT: entry:
51 // CHECK-NEXT: %x = alloca <[[#div(VBITS,32)]] x i32>, align 16
52 // CHECK-NEXT: %y = alloca <[[#div(VBITS,32)]] x i32>, align 16
53 // CHECK-NEXT: %retval.coerce = alloca <vscale x 4 x i32>, align 16
54 // CHECK-NEXT: %0 = bitcast <[[#div(VBITS,32)]] x i32>* %x to <vscale x 4 x i32>*
55 // CHECK-NEXT: store <vscale x 4 x i32> %x.coerce, <vscale x 4 x i32>* %0, align 16
56 // CHECK-NEXT: %x1 = load <[[#div(VBITS,32)]] x i32>, <[[#div(VBITS,32)]] x i32>* %x, align 16
57 // CHECK-NEXT: %1 = bitcast <[[#div(VBITS,32)]] x i32>* %y to <vscale x 4 x i32>*
58 // CHECK-NEXT: store <vscale x 4 x i32> %y.coerce, <vscale x 4 x i32>* %1, align 16
59 // CHECK-NEXT: %y2 = load <[[#div(VBITS,32)]] x i32>, <[[#div(VBITS,32)]] x i32>* %y, align 16
60 // CHECK-NEXT: %add = add <[[#div(VBITS,32)]] x i32> %y2, %x1
61 // CHECK-NEXT: %retval.0..sroa_cast = bitcast <vscale x 4 x i32>* %retval.coerce to <[[#div(VBITS,32)]] x i32>*
62 // CHECK-NEXT: store <[[#div(VBITS,32)]] x i32> %add, <[[#div(VBITS,32)]] x i32>* %retval.0..sroa_cast, align 16
63 // CHECK-NEXT: %2 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %retval.coerce, align 16
64 // CHECK-NEXT: ret <vscale x 4 x i32> %2
65 typedef svint32_t vec __attribute__((arm_sve_vector_bits(N)));
f(vec x,vec y)66 auto f(vec x, vec y) { return x + y; } // Returns a vec.
67 #endif
68
69 // Page 27, item 3, adapted for a generic value of __ARM_FEATURE_SVE_BITS
70 #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
71 #define N __ARM_FEATURE_SVE_BITS
72 typedef int16_t vec1 __attribute__((vector_size(N / 8)));
73 void f(vec1);
74 typedef svint16_t vec2 __attribute__((arm_sve_vector_bits(N)));
75 // CHECK-LABEL: define void @_Z1g9__SVE_VLSIu11__SVInt16_tLj
76 // CHECK-SAME: [[#VBITS]]
77 // CHECK-SAME: EE(<vscale x 8 x i16> %x.coerce)
78 // CHECK-NEXT: entry:
79 // CHECK128-NEXT: %x = alloca <[[#div(VBITS,16)]] x i16>, align 16
80 // CHECK128-NEXT: %0 = bitcast <[[#div(VBITS,16)]] x i16>* %x to <vscale x 8 x i16>*
81 // CHECK128-NEXT: store <vscale x 8 x i16> %x.coerce, <vscale x 8 x i16>* %0, align 16
82 // CHECK128-NEXT: %x1 = load <[[#div(VBITS,16)]] x i16>, <[[#div(VBITS,16)]] x i16>* %x, align 16
83 // CHECK128-NEXT: call void @_Z1fDv[[#div(VBITS,16)]]_s(<[[#div(VBITS,16)]] x i16> %x1)
84 // CHECK128-NEXT: ret void
85 // CHECKWIDE-NEXT: %x = alloca <[[#div(VBITS,16)]] x i16>, align 16
86 // CHECKWIDE-NEXT: %indirect-arg-temp = alloca <[[#div(VBITS,16)]] x i16>, align 16
87 // CHECKWIDE-NEXT: %0 = bitcast <[[#div(VBITS,16)]] x i16>* %x to <vscale x 8 x i16>*
88 // CHECKWIDE-NEXT: store <vscale x 8 x i16> %x.coerce, <vscale x 8 x i16>* %0, align 16
89 // CHECKWIDE-NEXT: %x1 = load <[[#div(VBITS,16)]] x i16>, <[[#div(VBITS,16)]] x i16>* %x, align 16
90 // CHECKWIDE-NEXT: store <[[#div(VBITS,16)]] x i16> %x1, <[[#div(VBITS,16)]] x i16>* %indirect-arg-temp, align 16
91 // CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS,16)]]_s(<[[#div(VBITS,16)]] x i16>* nonnull %indirect-arg-temp)
92 // CHECKWIDE-NEXT: ret void
g(vec2 x)93 void g(vec2 x) { f(x); } // OK
94 #endif
95