1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple armv8-arm-none-eabi \
3 // RUN: -target-feature +neon -target-feature +bf16 -mfloat-abi soft \
4 // RUN: -disable-O0-optnone -S -emit-llvm -o - %s \
5 // RUN: | opt -S -mem2reg -instcombine | FileCheck %s
6 // RUN: %clang_cc1 -triple armv8-arm-none-eabi \
7 // RUN: -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
8 // RUN: -disable-O0-optnone -S -emit-llvm -o - %s \
9 // RUN: | opt -S -mem2reg -instcombine | FileCheck %s
10
11 #include <arm_neon.h>
12
13 // CHECK-LABEL: @test_vbfdot_f32(
14 // CHECK-NEXT: entry:
15 // CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> [[R:%.*]], <4 x bfloat> [[A:%.*]], <4 x bfloat> [[B:%.*]]) [[ATTR3:#.*]]
16 // CHECK-NEXT: ret <2 x float> [[VBFDOT3_I]]
17 //
test_vbfdot_f32(float32x2_t r,bfloat16x4_t a,bfloat16x4_t b)18 float32x2_t test_vbfdot_f32(float32x2_t r, bfloat16x4_t a, bfloat16x4_t b) {
19 return vbfdot_f32(r, a, b);
20 }
21
22 // CHECK-LABEL: @test_vbfdotq_f32(
23 // CHECK-NEXT: entry:
24 // CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) [[ATTR3]]
25 // CHECK-NEXT: ret <4 x float> [[VBFDOT3_I]]
26 //
test_vbfdotq_f32(float32x4_t r,bfloat16x8_t a,bfloat16x8_t b)27 float32x4_t test_vbfdotq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b){
28 return vbfdotq_f32(r, a, b);
29 }
30
31 // CHECK-LABEL: @test_vbfdot_lane_f32(
32 // CHECK-NEXT: entry:
33 // CHECK-NEXT: [[DOTCAST:%.*]] = bitcast <4 x bfloat> [[B:%.*]] to <2 x float>
34 // CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[DOTCAST]], <2 x float> undef, <2 x i32> zeroinitializer
35 // CHECK-NEXT: [[DOTCAST1:%.*]] = bitcast <2 x float> [[LANE]] to <4 x bfloat>
36 // CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> [[R:%.*]], <4 x bfloat> [[A:%.*]], <4 x bfloat> [[DOTCAST1]]) [[ATTR3]]
37 // CHECK-NEXT: ret <2 x float> [[VBFDOT3_I]]
38 //
test_vbfdot_lane_f32(float32x2_t r,bfloat16x4_t a,bfloat16x4_t b)39 float32x2_t test_vbfdot_lane_f32(float32x2_t r, bfloat16x4_t a, bfloat16x4_t b){
40 return vbfdot_lane_f32(r, a, b, 0);
41 }
42
43 // CHECK-LABEL: @test_vbfdotq_laneq_f32(
44 // CHECK-NEXT: entry:
45 // CHECK-NEXT: [[DOTCAST:%.*]] = bitcast <8 x bfloat> [[B:%.*]] to <4 x float>
46 // CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[DOTCAST]], <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
47 // CHECK-NEXT: [[DOTCAST1:%.*]] = bitcast <4 x float> [[LANE]] to <8 x bfloat>
48 // CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[DOTCAST1]]) [[ATTR3]]
49 // CHECK-NEXT: ret <4 x float> [[VBFDOT3_I]]
50 //
test_vbfdotq_laneq_f32(float32x4_t r,bfloat16x8_t a,bfloat16x8_t b)51 float32x4_t test_vbfdotq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b) {
52 return vbfdotq_laneq_f32(r, a, b, 3);
53 }
54
55 // CHECK-LABEL: @test_vbfdot_laneq_f32(
56 // CHECK-NEXT: entry:
57 // CHECK-NEXT: [[DOTCAST:%.*]] = bitcast <8 x bfloat> [[B:%.*]] to <4 x float>
58 // CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[DOTCAST]], <4 x float> undef, <2 x i32> <i32 3, i32 3>
59 // CHECK-NEXT: [[DOTCAST1:%.*]] = bitcast <2 x float> [[LANE]] to <4 x bfloat>
60 // CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> [[R:%.*]], <4 x bfloat> [[A:%.*]], <4 x bfloat> [[DOTCAST1]]) [[ATTR3]]
61 // CHECK-NEXT: ret <2 x float> [[VBFDOT3_I]]
62 //
test_vbfdot_laneq_f32(float32x2_t r,bfloat16x4_t a,bfloat16x8_t b)63 float32x2_t test_vbfdot_laneq_f32(float32x2_t r, bfloat16x4_t a, bfloat16x8_t b) {
64 return vbfdot_laneq_f32(r, a, b, 3);
65 }
66
67 // CHECK-LABEL: @test_vbfdotq_lane_f32(
68 // CHECK-NEXT: entry:
69 // CHECK-NEXT: [[DOTCAST:%.*]] = bitcast <4 x bfloat> [[B:%.*]] to <2 x float>
70 // CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[DOTCAST]], <2 x float> undef, <4 x i32> zeroinitializer
71 // CHECK-NEXT: [[DOTCAST1:%.*]] = bitcast <4 x float> [[LANE]] to <8 x bfloat>
72 // CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[DOTCAST1]]) [[ATTR3]]
73 // CHECK-NEXT: ret <4 x float> [[VBFDOT3_I]]
74 //
test_vbfdotq_lane_f32(float32x4_t r,bfloat16x8_t a,bfloat16x4_t b)75 float32x4_t test_vbfdotq_lane_f32(float32x4_t r, bfloat16x8_t a, bfloat16x4_t b) {
76 return vbfdotq_lane_f32(r, a, b, 0);
77 }
78
79 // CHECK-LABEL: @test_vbfmmlaq_f32(
80 // CHECK-NEXT: entry:
81 // CHECK-NEXT: [[VBFMMLAQ_V3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfmmla(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) [[ATTR3]]
82 // CHECK-NEXT: ret <4 x float> [[VBFMMLAQ_V3_I]]
83 //
test_vbfmmlaq_f32(float32x4_t r,bfloat16x8_t a,bfloat16x8_t b)84 float32x4_t test_vbfmmlaq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b) {
85 return vbfmmlaq_f32(r, a, b);
86 }
87
88 // CHECK-LABEL: @test_vbfmlalbq_f32(
89 // CHECK-NEXT: entry:
90 // CHECK-NEXT: [[VBFMLALBQ_V3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) [[ATTR3]]
91 // CHECK-NEXT: ret <4 x float> [[VBFMLALBQ_V3_I]]
92 //
test_vbfmlalbq_f32(float32x4_t r,bfloat16x8_t a,bfloat16x8_t b)93 float32x4_t test_vbfmlalbq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b) {
94 return vbfmlalbq_f32(r, a, b);
95 }
96
97 // CHECK-LABEL: @test_vbfmlaltq_f32(
98 // CHECK-NEXT: entry:
99 // CHECK-NEXT: [[VBFMLALTQ_V3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) [[ATTR3]]
100 // CHECK-NEXT: ret <4 x float> [[VBFMLALTQ_V3_I]]
101 //
test_vbfmlaltq_f32(float32x4_t r,bfloat16x8_t a,bfloat16x8_t b)102 float32x4_t test_vbfmlaltq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b) {
103 return vbfmlaltq_f32(r, a, b);
104 }
105
106 // CHECK-LABEL: @test_vbfmlalbq_lane_f32(
107 // CHECK-NEXT: entry:
108 // CHECK-NEXT: [[VECINIT35:%.*]] = shufflevector <4 x bfloat> [[B:%.*]], <4 x bfloat> undef, <8 x i32> zeroinitializer
109 // CHECK-NEXT: [[VBFMLALBQ_V3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[VECINIT35]]) [[ATTR3]]
110 // CHECK-NEXT: ret <4 x float> [[VBFMLALBQ_V3_I]]
111 //
test_vbfmlalbq_lane_f32(float32x4_t r,bfloat16x8_t a,bfloat16x4_t b)112 float32x4_t test_vbfmlalbq_lane_f32(float32x4_t r, bfloat16x8_t a, bfloat16x4_t b) {
113 return vbfmlalbq_lane_f32(r, a, b, 0);
114 }
115
116 // CHECK-LABEL: @test_vbfmlalbq_laneq_f32(
117 // CHECK-NEXT: entry:
118 // CHECK-NEXT: [[VECINIT35:%.*]] = shufflevector <8 x bfloat> [[B:%.*]], <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
119 // CHECK-NEXT: [[VBFMLALBQ_V3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[VECINIT35]]) [[ATTR3]]
120 // CHECK-NEXT: ret <4 x float> [[VBFMLALBQ_V3_I]]
121 //
test_vbfmlalbq_laneq_f32(float32x4_t r,bfloat16x8_t a,bfloat16x8_t b)122 float32x4_t test_vbfmlalbq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b) {
123 return vbfmlalbq_laneq_f32(r, a, b, 3);
124 }
125
126 // CHECK-LABEL: @test_vbfmlaltq_lane_f32(
127 // CHECK-NEXT: entry:
128 // CHECK-NEXT: [[VECINIT35:%.*]] = shufflevector <4 x bfloat> [[B:%.*]], <4 x bfloat> undef, <8 x i32> zeroinitializer
129 // CHECK-NEXT: [[VBFMLALTQ_V3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[VECINIT35]]) [[ATTR3]]
130 // CHECK-NEXT: ret <4 x float> [[VBFMLALTQ_V3_I]]
131 //
test_vbfmlaltq_lane_f32(float32x4_t r,bfloat16x8_t a,bfloat16x4_t b)132 float32x4_t test_vbfmlaltq_lane_f32(float32x4_t r, bfloat16x8_t a, bfloat16x4_t b) {
133 return vbfmlaltq_lane_f32(r, a, b, 0);
134 }
135
136 // CHECK-LABEL: @test_vbfmlaltq_laneq_f32(
137 // CHECK-NEXT: entry:
138 // CHECK-NEXT: [[VECINIT35:%.*]] = shufflevector <8 x bfloat> [[B:%.*]], <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
139 // CHECK-NEXT: [[VBFMLALTQ_V3_I:%.*]] = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[VECINIT35]]) [[ATTR3]]
140 // CHECK-NEXT: ret <4 x float> [[VBFMLALTQ_V3_I]]
141 //
test_vbfmlaltq_laneq_f32(float32x4_t r,bfloat16x8_t a,bfloat16x8_t b)142 float32x4_t test_vbfmlaltq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b) {
143 return vbfmlaltq_laneq_f32(r, a, b, 3);
144 }
145