1 // RUN: %clang_cc1 -triple thumbv7-none-linux-gnueabihf \
2 // RUN: -target-abi aapcs \
3 // RUN: -target-cpu cortex-a7 \
4 // RUN: -mfloat-abi hard \
5 // RUN: -ffreestanding \
6 // RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
7
8 #include <arm_neon.h>
9
10 // CHECK-LABEL: define <2 x float> @test_fma_order(<2 x float> %accum, <2 x float> %lhs, <2 x float> %rhs) #0 {
11 // CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %rhs, <2 x float> %accum) #3
12 // CHECK: ret <2 x float> [[TMP6]]
test_fma_order(float32x2_t accum,float32x2_t lhs,float32x2_t rhs)13 float32x2_t test_fma_order(float32x2_t accum, float32x2_t lhs, float32x2_t rhs) {
14 return vfma_f32(accum, lhs, rhs);
15 }
16
17 // CHECK-LABEL: define <4 x float> @test_fmaq_order(<4 x float> %accum, <4 x float> %lhs, <4 x float> %rhs) #1 {
18 // CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %rhs, <4 x float> %accum) #3
19 // CHECK: ret <4 x float> [[TMP6]]
test_fmaq_order(float32x4_t accum,float32x4_t lhs,float32x4_t rhs)20 float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t rhs) {
21 return vfmaq_f32(accum, lhs, rhs);
22 }
23
24 // CHECK-LABEL: define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 {
25 // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0
26 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1
27 // CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
28 // CHECK: [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8>
29 // CHECK: [[TMP3:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 x float> [[VECINIT1_I]], <2 x float> %a)
30 // CHECK: ret <2 x float> [[TMP3]]
test_vfma_n_f32(float32x2_t a,float32x2_t b,float32_t n)31 float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) {
32 return vfma_n_f32(a, b, n);
33 }
34
35 // CHECK-LABEL: define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #1 {
36 // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
37 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1
38 // CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %n, i32 2
39 // CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %n, i32 3
40 // CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
41 // CHECK: [[TMP2:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <16 x i8>
42 // CHECK: [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> [[VECINIT3_I]], <4 x float> %a)
43 // CHECK: ret <4 x float> [[TMP3]]
test_vfmaq_n_f32(float32x4_t a,float32x4_t b,float32_t n)44 float32x4_t test_vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n) {
45 return vfmaq_n_f32(a, b, n);
46 }
47
48 // CHECK: attributes #0 ={{.*}}"min-legal-vector-width"="64"
49 // CHECK: attributes #1 ={{.*}}"min-legal-vector-width"="128"
50