1 //===-- RegisterInfoPOSIX_arm64.h -------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H 10 #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H 11 12 #include "RegisterInfoAndSetInterface.h" 13 #include "lldb/Target/RegisterContext.h" 14 #include "lldb/lldb-private.h" 15 #include <map> 16 17 enum class SVEState { Unknown, Disabled, FPSIMD, Full }; 18 19 class RegisterInfoPOSIX_arm64 20 : public lldb_private::RegisterInfoAndSetInterface { 21 public: 22 enum { GPRegSet = 0, FPRegSet, SVERegSet }; 23 24 // AArch64 Register set FP/SIMD feature configuration 25 enum { 26 eVectorQuadwordAArch64, 27 eVectorQuadwordAArch64SVE, 28 eVectorQuadwordAArch64SVEMax = 256 29 }; 30 31 // based on RegisterContextDarwin_arm64.h 32 LLVM_PACKED_START 33 struct GPR { 34 uint64_t x[29]; // x0-x28 35 uint64_t fp; // x29 36 uint64_t lr; // x30 37 uint64_t sp; // x31 38 uint64_t pc; // pc 39 uint32_t cpsr; // cpsr 40 }; 41 LLVM_PACKED_END 42 43 // based on RegisterContextDarwin_arm64.h 44 struct VReg { 45 uint8_t bytes[16]; 46 }; 47 48 // based on RegisterContextDarwin_arm64.h 49 struct FPU { 50 VReg v[32]; 51 uint32_t fpsr; 52 uint32_t fpcr; 53 }; 54 55 // based on RegisterContextDarwin_arm64.h 56 struct EXC { 57 uint64_t far; // Virtual Fault Address 58 uint32_t esr; // Exception syndrome 59 uint32_t exception; // number of arm exception token 60 }; 61 62 // based on RegisterContextDarwin_arm64.h 63 struct DBG { 64 uint64_t bvr[16]; 65 uint64_t bcr[16]; 66 uint64_t wvr[16]; 67 uint64_t wcr[16]; 68 uint64_t mdscr_el1; 69 }; 70 71 RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch); 72 73 size_t GetGPRSize() const override; 74 75 size_t GetFPRSize() const override; 76 77 const lldb_private::RegisterInfo *GetRegisterInfo() const override; 78 79 uint32_t GetRegisterCount() const override; 80 81 const lldb_private::RegisterSet * 82 GetRegisterSet(size_t reg_set) const override; 83 84 size_t GetRegisterSetCount() const override; 85 86 size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override; 87 88 uint32_t ConfigureVectorRegisterInfos(uint32_t mode); 89 VectorSizeIsValid(uint32_t vq)90 bool VectorSizeIsValid(uint32_t vq) { 91 if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax) 92 return true; 93 return false; 94 } 95 IsSVEEnabled()96 bool IsSVEEnabled() const { return m_vector_reg_vq > eVectorQuadwordAArch64; } 97 98 bool IsSVEZReg(unsigned reg) const; 99 bool IsSVEPReg(unsigned reg) const; 100 bool IsSVERegVG(unsigned reg) const; 101 102 uint32_t GetRegNumSVEZ0() const; 103 uint32_t GetRegNumSVEFFR() const; 104 uint32_t GetRegNumFPCR() const; 105 uint32_t GetRegNumFPSR() const; 106 uint32_t GetRegNumSVEVG() const; 107 108 private: 109 typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>> 110 per_vq_register_infos; 111 112 per_vq_register_infos m_per_vq_reg_infos; 113 114 uint32_t m_vector_reg_vq = eVectorQuadwordAArch64; 115 116 const lldb_private::RegisterInfo *m_register_info_p; 117 uint32_t m_register_info_count; 118 }; 119 120 #endif 121